MC68EN360CAI25L Freescale Semiconductor, MC68EN360CAI25L Datasheet - Page 490

• Manufacturer Part Number: MC68EN360CAI25L
• Description: IC MPU QUICC 25MHZ 240-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MC68000r

Specifications of MC68EN360CAI25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Core Size: 32 Bit
• Cpu Speed: 25MHz
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: FQFP
• No. Of Pins: 240
• Supply Voltage Range: 4.75V To 5.25V
• Rohs Compliant: Yes
• Family Name: M68xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

Serial Communication Controllers (SCCs)
GLt—Glitch on Tx
AB—Auto Baud
IDL—Idle Sequence Status Changed
GRA—Graceful Stop Complete
BRKe—Break End
BRKs—Break Start
CCR—Control Character Received
BSY—Busy Condition
TX—Tx Buffer
RX—Rx Buffer
7-166
A clock glitch was detected by this SCC on the transmit clock.
An auto baud lock was detected. The CPU32+ core should rewrite the baud rate genera-
tor with the precise divider value for the desired baud rate. See 7.9 Baud Rate Generators
(BRGs) for more details.
A change in the status of the serial line was detected on the UART channel. The real-time
status of the line may be read in SCCS. Idle is entered when one character of all ones is
received. It is exited when a single zero is received.
A graceful stop, which was initiated by the GRACEFUL STOP TRANSMIT command, is
now complete. This bit is set as soon the transmitter has finished transmitting any buffer
that was in progress when the command was issued. It will be set immediately if no buffer
was in progress when the command was issued.
The end of a break sequence was detected. This indication will be set no sooner than after
one idle bit is received following a break sequence.
A break character was received. This is the first break of a break sequence. The user will
not receive multiple BRKs events if a long break sequence is received.
A control character was received (with reject (R) character = 1) and stored in the receive
control character register (RCCR).
A character was received and discarded due to lack of buffers. If the multidrop mode is
selected, the receiver automatically enters hunt mode immediately. Otherwise, reception
continues as soon as an empty buffer is provided. The latest that an Rx BD can be made
empty (have its E-bit set) and still guarantee avoiding the busy condition is the middle of
the stop bit of the first character to be stored in that buffer.
A buffer has been transmitted over the UART channel. If CR = 1 in the Tx BD, this bit is
set no sooner than when the last stop bit of the last character in the buffer begins to be
transmitted. If CR = 0, this bit is set after the last character was written to the transmit
FIFO.
A buffer has been received over the UART channel. This event occurs no sooner than the
middle of the first stop bit of the character that caused the buffer to be closed.
Freescale Semiconductor, Inc.
For More Information On This Product,
MC68360 USER’S MANUAL
Go to: www.freescale.com