MC68EN360CAI25L Freescale Semiconductor, MC68EN360CAI25L Datasheet - Page 442

• Manufacturer Part Number: MC68EN360CAI25L
• Description: IC MPU QUICC 25MHZ 240-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MC68000r

Specifications of MC68EN360CAI25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Core Size: 32 Bit
• Cpu Speed: 25MHz
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: FQFP
• No. Of Pins: 240
• Supply Voltage Range: 4.75V To 5.25V
• Rohs Compliant: Yes
• Family Name: M68xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

Serial Communication Controllers (SCCs)
RDCR—Receive DPLL Clock Rate
RENC—Receiver Decoding Method
TENC—Transmitter Encoding Method
DIAG—Diagnostic Mode
7-118
The RDCR bits determine the divider rate of the receive DPLL. If the DPLL is not used,
the 1 value should be chosen, except in asynchronous UART mode where 8 , 16 , or
32 must be chosen. The user should program RDCR to equal TDCR in most applica-
tions.
If the DPLL is used in the application, the selection of RDCR depends on the encoding.
NRZI usualy requires 1 ; whereas, FM0/FM1, Manchester, and Differential Manchester
allow 8 , 16 , or 32 . The 8 option allows highest speed; whereas, the 32 option pro-
vides the greatest resolution.
Select NRZ if the DPLL is not used. The user should program RENC to equal TENC in
most applications. Do not use this internal DPLL for Ethernet mode.
Select NRZ if the DPLL is not used. The user should program TENC to equal RENC in
most applications. Do not use this internal DPLL for Ethernet mode.
In normal operation mode, the SCC operates normally. The receive data enters the RXD
pin and the transmit data is shifted out through the TXD pin. The SCC uses the modem
signals (CD and CTS) to automatically enable and disable transmission and reception.
These timings are shown in 7.10.11 SCC Timing Control.
In local loopback mode, the transmitter output is internally connected to the receiver input,
while the receiver and the transmitter operate normally. The value on the RXD pin is ig-
00 = 1 clock mode (only NRZ or NRZI decodings are allowed.)
01 = 8 clock mode
10 = 16 clock mode (normally chosen for UART and AppleTalk)
11 = 32 clock mode
000 = NRZ (default setting if DPLL is not used)
001 = NRZI Mark (set RINV also for NRZI Space)
010 = FM0 (set RINV also for FM1)
011 = Reserved
100 = Manchester
101 = Reserved
110 = Differential Manchester (Differential Biphase-L)
111 = Reserved
000 = NRZ (default setting if DPLL is not used)
001 = NRZI Mark (set TINV also for NRZI Space)
010 = FM0 (set TINV also for FM1)
011 = Reserved
100 = Manchester
101 = Reserved
110 = Differential Manchester (Differential Biphase-L)
111 = Reserved
00 =Normal operation (CTS and CD signals under automatic control)
Freescale Semiconductor, Inc.
For More Information On This Product,
MC68360 USER’S MANUAL
Go to: www.freescale.com