MC68EN360CAI25L Freescale Semiconductor, MC68EN360CAI25L Datasheet - Page 761

• Manufacturer Part Number: MC68EN360CAI25L
• Description: IC MPU QUICC 25MHZ 240-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MC68000r

Specifications of MC68EN360CAI25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Core Size: 32 Bit
• Cpu Speed: 25MHz
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: FQFP
• No. Of Pins: 240
• Supply Voltage Range: 4.75V To 5.25V
• Rohs Compliant: Yes
• Family Name: M68xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

Freescale Semiconductor, Inc.
Applications
9.4.2.4 FLASH EPROM. Figure 9-11 shows the interface to flash EPROM devices. In this
design, the assumption is made that only the MC68EC040 will access this array. The
inverter is only required if DRAM is used elsewhere in the system, since the OE function is
lost when the AMUX pin is used. This design assumes that the write operations are CE con-
trolled, rather than WE controlled. Most flash EPROM manufacturers now support this alter-
native timing method.
9.4.2.5 REGULAR SRAM. Figure 9-12 shows the interface to SRAM. In this design, both
the MC68EC040 and the QUICC may access the SRAM array. The inverter is only required
if DRAM is used elsewhere in the system, since the OE function is lost when the AMUX pin
is used. This design also allows the QUICC to support bursting by the MC68EC040 using
the BADD3–BADD2 signals. The QUICC also uses these signals as A3–A2 address lines
during its normal SRAM accesses. If MC68EC040 bursting is not supported, the BADD3–
BADD2 signals can be replaced with the A3–A2 signals.
9.4.2.6 BURST SRAM. Figure 9-13 shows the interface to Motorola's 32K 9 MCM62940A
bursting SRAM. This can provide better memory throughput speeds than the regular SRAM
array. Figure 9-13 shows the solution for an array that is accessed by the MC68EC040 and
the QUICC.
To speed access times, the chip select pin (S0) of the burst SRAM is connected directly to
the A27 pin of the system bus. This gives half of the usable address space to this array,
although this should not be a problem in most systems considering the 28 address pins
available. No chip select pin from the QUICC is used.
The inverter on the R/W signal is only required if DRAM is used elsewhere in the system,
since the OE function is lost when the AMUX pin is used. The CLKO1 signal is derived
directly from the QUICC CLKO1 pin. Parity is also supported in the array, using the PRTY3–
PRTY0 signals on the system bus.
Although not used in this design, Motorola also offers a larger version of the MCM62940A,
called the MCM67M618, that is organized into a 64K
18 array.
In Figure 9-13, the TSC pin is connected to the AS pin to handle the QUICC accesses. The
QUICC accesses do not use the bursting feature of the MCM62940A. BAA, which could be
asserted during the QUICC accesses due to the QUICC DSACK1 being multiplexed with the
MC68EC040 TA, is a don't care as long as TSC remains low. After TSC negated, the OE
and WE signals are negated, disabling the MC62940A burst
9-41
MC68360 USER’S MANUAL
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