MC68EN360CAI25L Freescale Semiconductor, MC68EN360CAI25L Datasheet - Page 949

• Manufacturer Part Number: MC68EN360CAI25L
• Description: IC MPU QUICC 25MHZ 240-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MC68000r

Specifications of MC68EN360CAI25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Core Size: 32 Bit
• Cpu Speed: 25MHz
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: FQFP
• No. Of Pins: 240
• Supply Voltage Range: 4.75V To 5.25V
• Rohs Compliant: Yes
• Family Name: M68xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

IDMA Bus Arbitration (Normal Operation) 7-
IDMA Buffer Descriptors 7-36
IDMA Bus Arbitration 7-43, 7-44
IDMA Channels 7-24
IDMA Controller Block Diagram 7-25
IDMA Controllers 7-24
IDMA Examples 7-55
IDMA Operand Transfers 7-45
IDMA Registers 7-26
IEEE 802.3 7-235
IFETCH 2-11, 5-60, 5-63, 5-80, 5-82
IMB 1-4, 10
Immediate Arithmetic/logic Instruction Table
IN 5-49, 5-50, 5-52
INIT RX PARAMETERS 7-149, 7-176, 7-
INIT RX PARAMETERS 7-280
INIT TX AND RX PARAMETERS Command
INIT TX PARAMETERS 7-148, 7-205, 7-
INIT_IDMA 7-38
Initialization 9-10
In-Line Synchronization Pattern 7-223
Instruction Execution Overlap 5-85, 5-86
Instruction Execution Time Calculation 5-86
Instruction Pipeline Operation 5-85
Intel 7-126, 7-272, 7-321
Interface Multiple QUICCs to an
Dual Address Destination Write 7-46
Dual Address Mode 7-45
Dual Address Packing 7-46
Dual Address Source Read 7-45
Dual Address Transfer Example 7-46
External Burst Requests 7-40
External Cycle Steal 7-42
Fast-Termination Option 7-50
IDMA Bus Arbitration 7-43
IDMA Channels 7-24
IDMA Controller Block Diagram 7-25
IDMA Examples 7-55
IDMA Operand Transfers 7-45
Requesting IDMA Transfers 7-39
Single Address Mode 7-48
Single Address Transfer 7-48
44
5-95
206, 7-227, 7-251, 7-297, 7-323
7-307
227, 7-251, 7-280, 7-297, 7-323
Freescale Semiconductor, Inc.
For More Information On This Product,
MC68356 USER’S MANUAL
Go to: www.freescale.com
Interface Signals 7-33
Interlocked Data Transfers 7-333
Intermodule Bus 1-4, 10
Internal Accesses 4-59
Internal and External Loopback 7-255
Internal Exceptions 5-36
Internal Memory 3-1
Internal Registers Memory Map 3-4
Interpacket Gap Time 7-254
Interrupt 6-26, 7-370, 9-16, 9-23, 9-34
Interrupt Acknowledge 4-36
Interrupt Arbitration 6-8, 6-33
Interrupt Exceptions 5-38
Interrupt Generation 6-6
Interrupt Handler Examples 7-382
Autovector 4-6, 4-38
CPM Interrupt Controller 7-370
Grouped 7-380
HDLC Interrupt 7-185
Highest Priority 7-380
Interrupt Acknowledge 4-36
Interrupt Arbitration 6-8, 6-33
Interrupt Handler Examples 7-382
Interrupt In-Service Register 7-381
Interrupt Mask Register 7-381
Interrupt Pending Register 7-380
Interrupt Service Mask 6-33
Interrupt Source Priorities 7-373
Interrupt Vector 6-8
Interrupt Vector Generation 7-376
Interrupts from the SCCs 7-128
IRQx 7-379
Masking Interrupt Sources 7-375
Nested Interrupts 7-374
Periodic Interrupt Request Level
QUICC Interrupt Structure 7-372
RXF Interrupt 7-174
SCC Interrupt Handling 7-130
Slave Mode 6-26
SMC Interrupt Handling 7-305
SMC UART 7-289
Spread 7-380
Spurious Interrupt 4-41
UART Interrupt Events Example 7-165
Vector Base Address 7-380
MC68EC040 9-51
Encoding 6-37
Index