MC68EN360CAI25L Freescale Semiconductor, MC68EN360CAI25L Datasheet - Page 354

• Manufacturer Part Number: MC68EN360CAI25L
• Description: IC MPU QUICC 25MHZ 240-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MC68000r

Specifications of MC68EN360CAI25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Core Size: 32 Bit
• Cpu Speed: 25MHz
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: FQFP
• No. Of Pins: 240
• Supply Voltage Range: 4.75V To 5.25V
• Rohs Compliant: Yes
• Family Name: M68xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

IDMA Channels
BT — Burst Transfer
RST—Software Reset
STR—Start Operation
7.6.2.3 SOURCE ADDRESS POINTER REGISTER (SAPR). The
address bits of the source operand used by the IDMA to access memory or memory-
mapped peripheral controller registers. During the IDMA read cycle, the address on the
master address bus is driven from this register. The SAPR may be programmed by the SAPI
bits to be incremented or remain constant after each operand transfer.
7-30
The BT bits control the maximum percentage of the IMB that the IDMA can use during
each 1024 clock cycle period after enabling the IDMA.
This bit resets the IDMA to the same state as an external reset. The IDMA clears RST
when the reset is complete.
This bit starts the IDMA transfer if the REQG bits are programmed for an internal request.
If the REQG bits are programmed for an external request, this bit must be set before the
IDMA will recognize the first request on the DREQx input.
00 = IDMA gets up to 75% of the bus bandwidth.
01 = IDMA gets up to 50% of the bus bandwidth.
10 = IDMA gets up to 25% of the bus bandwidth.
11 = IDMA gets up to 12.5% of the bus bandwidth.
0 = Normal operation.
1 = The channel aborts any external pending or running bus cycles and terminates
0 = Stop channel. Clearing this bit causes the IDMA to stop transferring data at the end
1 = Start channel. Setting this bit allows the IDMA to start transferring data (or continue
channel operation. Setting RST clears all bits in the CSR and CMR.
of the current bus cycle. The IDMA internal state is not altered.
if previously stopped).
These percentages are valid only when using internal request
generation (REQG = 00).
The user should reset the IDMA channel prior to issuing the LP-
STOP instruction.
STR is cleared automatically when the transfer is complete.
If the STR bit is cleared by software during the middle of an
IDMA operand transfer, the IDMA will continue to hold the bit in
a one state until the operand transfer has completed. Thus, if the
user waits for the STR bit to be cleared after clearing it in soft-
ware, he is assured that the values of SAPR, DAPR, and BCR
accurately show the current state of the IDMA transfer.
Freescale Semiconductor, Inc.
For More Information On This Product,
MC68360 USER’S MANUAL
Go to: www.freescale.com
NOTES
NOTE
NOTE
SAPR
contains
32