MC68EN360CAI25L Freescale Semiconductor, MC68EN360CAI25L Datasheet - Page 227

• Manufacturer Part Number: MC68EN360CAI25L
• Description: IC MPU QUICC 25MHZ 240-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MC68000r

Specifications of MC68EN360CAI25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Core Size: 32 Bit
• Cpu Speed: 25MHz
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: FQFP
• No. Of Pins: 240
• Supply Voltage Range: 4.75V To 5.25V
• Rohs Compliant: Yes
• Family Name: M68xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

Freescale Semiconductor, Inc.
CPU32+
5.7.1.3.3 Microbus Controller. The microbus controller performs bus cycles issued by the
microsequencer. Operand accesses always have priority over instruction prefetches. Word
and byte operands are accessed in a single CPU-initiated bus cycle, although the external
bus interface may be required to initiate a second cycle when a word operand is sent to a
byte-sized external port. If long operands are accessed from a 16-bit port, they are accessed
in two bus cycles, most significant word first.
The instruction pipeline is capable of recognizing instructions that cause a change of flow.
It informs the bus controller when a change of flow is imminent, and the bus controller
refrains from starting prefetches that would be discarded due to the change of flow.
5.7.1.4 INSTRUCTION EXECUTION OVERLAP. Overlap is the time, measured in clock
cycles, that an instruction executes concurrently with the previous instruction. As shown in
Figure 5-31, portions of instructions A and B execute simultaneously, reducing total execu-
tion time. Because portions of instructions B and C also overlap, overall execution time for
all three instructions is also reduced.
Each instruction contributes to the total overlap time. The portion of execution time at the
end of instruction A that can overlap the beginning of instruction B is called the tail of instruc-
tion A. The portion of execution time at the beginning of instruction B that can overlap the
end of instruction A is called the head of instruction B. The total overlap time between in-
structions A and B is the smaller tail of A and the head of B.
INSTRUCTION A
INSTRUCTION B
INSTRUCTION C
OVERLAP
OVERLAP
Figure 5-31. Simultaneous Instruction Execution
The execution time attributed to instructions A, B, and C after considering the overlap is illus-
trated in Figure 5-32. The overlap time is attributed to the execution time of the completing
instruction. The following equation shows the method for calculating the overlap time:
Overlap = min (Tail
, Head
)
N
N+1
MC68360 USER’S MANUAL
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