MC68EN360CAI25L Freescale Semiconductor, MC68EN360CAI25L Datasheet - Page 645

• Manufacturer Part Number: MC68EN360CAI25L
• Description: IC MPU QUICC 25MHZ 240-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MC68000r

Specifications of MC68EN360CAI25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Core Size: 32 Bit
• Cpu Speed: 25MHz
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: FQFP
• No. Of Pins: 240
• Supply Voltage Range: 4.75V To 5.25V
• Rohs Compliant: Yes
• Family Name: M68xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

RAM values will not normally need to be accessed by user software. They should only be
modified when no SPI activity is in progress.
7.12.5.3.1 BD Table Pointer (RBASE, TBASE). The RBASE and TBASE entries define
the starting location in the dual-port RAM for the set of BDs for receive and transmit func-
tions of the SPI. This provides a great deal of flexibility in how BDs for an SPI are partitioned.
By setting the W-bit in the last BD in each BD list, the user may select how many BDs to
allocate for the transmit and receive side of the SPI. The user must initialize these entries
before enabling the SPI. Furthermore, the user should not configure BD tables of the SPI to
overlap any other serial channel’s BDs, or erratic operation will occur.
7.12.5.3.2 SPI Function Code Registers (RFCR, TFCR). The FC entry contains the value
that the user would like to appear on the function code pins (FC3–FC0), when the associ-
ated SDMA channel accesses memory. It also controls the byte-ordering convention to be
used in the transfers.
Receive Function Code Register
Bits 7–5—Reserved
MOT—Motorola
FC3–FC0—Function Code 3–0
Transmit Function Code Register
These bits should be set to zero by the user.
This bit should be set by the user to achieve normal operation. MOT must be set if the
data buffer is located in external memory and has a 16-bit wide memory port size.
These bits contain the function code value used during this SDMA channel’s memory ac-
cesses. The user should write bit FC3 with a one to identify this SDMA channel access as
a DMA-type access. Example: FC3–FC0 = 1000. To keep interrupt acknowledge cycles
unique in the system, do not write the value 0111 binary to these bits.
0 = DEC and Intel convention is used for byte ordering—swapped operation. It is also
1 = Motorola byte ordering—normal operation. It is also called big-endian byte order-
called little-endian byte ordering. The bytes stored in each buffer word are reversed
as compared to the Motorola mode.
ing. As data is received from the serial line and put into the buffer, the most signif-
icant byte of the buffer word contains data received earlier than the least significant
byte of the same buffer word.
RBASE and TBASE should contain a value that is divisible by 8.
Freescale Semiconductor, Inc.
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For More Information On This Product,
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MC68360 USER’S MANUAL
Go to: www.freescale.com
5
5
MOT
MOT
NOTE
4
4
3
3
2
2
FC 3–FC0
FC3–FC0
1
1
Serial Peripheral Interface (SPI)
0
0