MC68EN360CAI25L Freescale Semiconductor, MC68EN360CAI25L Datasheet - Page 503

• Manufacturer Part Number: MC68EN360CAI25L
• Description: IC MPU QUICC 25MHZ 240-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MC68000r

Specifications of MC68EN360CAI25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Core Size: 32 Bit
• Cpu Speed: 25MHz
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: FQFP
• No. Of Pins: 240
• Supply Voltage Range: 4.75V To 5.25V
• Rohs Compliant: Yes
• Family Name: M68xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

DRT—Disable Receiver While Transmitting
BUS—HDLC Bus Mode
BRM—HDLC Bus RTS Mode
MFF—Multiple Frames in FIFO
7.10.17.9 HDLC RECEIVE BUFFER DESCRIPTOR (RX BD). The HDLC controller uses
the Rx BD to report information about the received data for each buffer. An example of the
Rx BD process is shown in Figure 7-52.
This bit is only valid if BUS = 1; otherwise, it is ignored.
0 = Normal operation
1 = While data is being transmitted by the SCC, the receiver is disabled, being gated
0 = Normal HDLC operation
1 = HDLC Bus operation selected. See 7.10.18 HDLC Bus Controller for more details.
0 = Normal RTS operation during HDLC Bus mode. RTS is asserted on the first bit of
1 = Special RTS operation during HDLC Bus mode. RTS is delayed by one bit with re-
0 = Normal operation. The transmit FIFO can never contain more than one HDLC
1 = The transmit FIFO can contain multiple frames, but CTS lost is not guaranteed to
by the internal RTS signal. This configuration is useful if the HDLC channel is con-
figured onto a multidrop line and the user does not wish to receive his own trans-
mission.
the transmit frame and negated after the first collision bit is received.
spect to the normal case. This is useful when the HDLC Bus protocol is run locally,
and at the same time, transmitted over a long-distance transmission line. Data may
be delayed by one bit before it is sent over the transmission line; thus, RTS may
be used to enable the transmission line buffers. The result is a clean signal level
sent over the transmission line.
frame. The CTS lost status will be reported accurately on a per-frame basis. The
receiver is not affected by this bit.
be reported on the exact buffer/frame on which it truly occurred. This option, how-
ever, can improve the performance of HDLC transmissions in cases of small back-
to-back frames or in cases where the user desires to strongly limit the number of
flags transmitted between frames. The receiver is not affected by this bit.
Freescale Semiconductor, Inc.
For More Information On This Product,
MC68360 USER’S MANUAL
Go to: www.freescale.com
Serial Communication Controllers (SCCs)