MC68EN360CAI25L Freescale Semiconductor, MC68EN360CAI25L Datasheet - Page 590

• Manufacturer Part Number: MC68EN360CAI25L
• Description: IC MPU QUICC 25MHZ 240-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MC68000r

Specifications of MC68EN360CAI25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Core Size: 32 Bit
• Cpu Speed: 25MHz
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: FQFP
• No. Of Pins: 240
• Supply Voltage Range: 4.75V To 5.25V
• Rohs Compliant: Yes
• Family Name: M68xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

Serial Communication Controllers (SCCs)
7.10.23.23 SCC ETHERNET EXAMPLE. The following list is an initialization sequence for
an Ethernet channel. SCC1 is used. The CLK1 pin is used for the Ethernet receiver, and the
CLK2 pin is used for the Ethernet transmitter.
7-266
1. The SDCR (SDMA Configuration Register) should be initialized to $0740, rather than
2. Configure the port A pins to enable the TXD1 and RXD1 pins. Write PAPAR bits 0
3. Configure the port C pins to enable CTS1 (CLSN) and CD1 (RENA). Write
4. Do not enable the RTS1 (TENA) pin yet because the pin is still functioning as RTS
5. Configure port A to enable the CLK1 and CLK2 pins. Write PAPAR bits 8 and 9
6. Connect the CLK1 and CLK2 pins to SCC1 using the SI. Write the R1CS bits in
7. Connect the SCC1 to the NMSI (i.e., its own set of pins). Clear the SC1
8. Write RBASE and TBASE in the SCC parameter RAM to point to the Rx BD and
9. Program the CR to execute the INIT RX & TX PARAMS command for this channel.
10. Write RFCR with $18 and TFCR with $18 for normal operation.
11. Write MRBLR with the maximum number of bytes per receive buffer. For this case,
12. Write C_PRES with $FFFFFFFF to comply with 32-bit CCITT-CRC.
13. Write C_MASK with $DEBB20E3 to comply with 32-bit CCITT-CRC.
14. Clear CRCEC, ALEC, and DISFC for the sake of clarity.
15. Write PAD with $8888 for the PAD value.
16. Write RET_Lim with $000F.
17. Write MFLR with $05EE to make the maximum frame size 1518 bytes.
18. Write MINFLR with $0040 to make the minimum frame size 64 bytes.
19. Write MAXD1 and MAXD2 with $05EE to make the maximum DMA count 1518
being left at its default value of $0000.
and 1 with ones. Write PADIR bits 0 and 1 with zeros. Write PAODR bit 1 with
zero.
PCPAR bits 4 and 5 with zeros. Write PCDIR bits 4 and 5 with zero. Write PCSO
bits 4 and 5 with ones.
(inactive in the high state), and transmission on the LAN could accidentally begin.
with a ones. Write PADIR bits 8 and 9 with zeros.
SICR to 101. Write the T1CS bits in SICR to 100.
bit in the SICR.
Tx BD in the dual-port RAM. Assuming one Rx BD at the beginning of dual-port
RAM, and one Tx BD following that Rx BD, write RBASE with $0000 and TBASE
with $0008.
For instance, to execute this command for SCC1, write $0001 to the CR. This com-
mand causes the RBPTR and TBPTR parameters of the serial channel to be updated
with the new values just programmed into RBASE and TBASE.
assume 1520 bytes, so MRBLR = $05F0. (In this example, the user wants to
receive an entire frame into one buffer, so the MRBLR value is simply chosen to be
the first value larger than 1518 that is evenly divisible by 4).
bytes.
Freescale Semiconductor, Inc.
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MC68360 USER’S MANUAL
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