MC68EN360CAI25L Freescale Semiconductor, MC68EN360CAI25L Datasheet - Page 235

• Manufacturer Part Number: MC68EN360CAI25L
• Description: IC MPU QUICC 25MHZ 240-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MC68000r

Specifications of MC68EN360CAI25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Core Size: 32 Bit
• Cpu Speed: 25MHz
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: FQFP
• No. Of Pins: 240
• Supply Voltage Range: 4.75V To 5.25V
• Rohs Compliant: Yes
• Family Name: M68xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

5.7.2.5 ARITHMETIC/LOGIC INSTRUCTIONS. The arithmetic/logic instruction table indi-
cates the number of clock periods needed to perform the specified arithmetic/logical instruc-
tion using the specified addressing mode. Footnotes indicate when to account for the
appropriate EA times. The total number of clock cycles is outside the parentheses. The num-
EXG
MOVEC Cr, Rn
MOVEC Rn, Cr
MOVE
MOVE
MOVE
MOVE
MOVE
MOVE
MOVE
MOVE
MOVEM.W CEA , RL
MOVEP.W(d
MOVEP.LDn, (d
MOVEP.L(d
MOVES (Save) CEA , Rn
MOVES (Op) CEA , Rn
1. The MOVES instruction has an additional save step that other instructions do not have. To
2. Timing is calculated with the CPU32+ in 16-bit mode.
MOVEM.WRL, CEA
MOVEM.L CEA , RL
MOVEM.LRL, CEA
MOVEP.WDn, (d
MOVES (Save)Rn, CEA
MOVES (Op)Rn, CEA
MOVE
MOVE
SWAP
X
Cr
n
RL
calculate the total instruction time, calculate the save, the EA, and the operation execution
times, and combine in the order listed, using the equations given in 5.7.1 Resource Schedul-
ing.
=
There is one bus cycle for byte and word operands and two bus cycles for long
operands. For long bus cycles, add two clocks to the tail and to the number of
cycles.
Each bus cycle may take up to four clocks without increasing total execution time.
Control registers USP, VBR, SFC, and DFC
Number of registers to transfer
Register List
Maximum time (certain data or mode combinations may execute faster).
Rn, Rm
CCR, Dn
CCR, CEA
Dn, CCR
SR, Dn
SR, CEA
Dn, SR
USP, An
An, USP
Dn
NOTES:
FEA , CCR
FEA , SR
16
16
, An), Dn
, An), Dn
16
Instruction
16
, An)
Freescale Semiconductor, Inc.
, An)
For More Information On This Product,
MC68360 USER’S MANUAL
Go to: www.freescale.com
Head
10
12
2
2
0
2
2
0
2
1
2
1
0
4
0
1
1
1
1
1
7
1
9
0
0
4
Tail
0
0
0
0
2
0
0
0
2
0
0
0
2
0
2
0
2
1
1
1
2
0
0
0
2
2
12
8
10 n
8
n
n
14-16(0/1/0)
n
11(X/1/0)
12(0/1/X)
14(0/2/0)
10(0/3/0)
10(0/3/0)
10(0/2/2)
11(2/2/0)
14(0/2/4)
19(4/2/0)
4(0/1/0)
4(0/1/0)
4(0/1/1)
4(0/1/0)
4(0/1/0)
4(0/1/0)
4(0/1/1)
3(0/1/0)
3(0/1/0)
2(0/1/0)
2(0/1/0)
6(0/1/0)
Cycles
4(n
4(2n
4(0, 2, n)
4 (0, 2, 2n)
1, 2, 0)
2, 2, 0)
CPU32+