MC68EN360CAI25L Freescale Semiconductor, MC68EN360CAI25L Datasheet - Page 272

• Manufacturer Part Number: MC68EN360CAI25L
• Description: IC MPU QUICC 25MHZ 240-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MC68000r

Specifications of MC68EN360CAI25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Core Size: 32 Bit
• Cpu Speed: 25MHz
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: FQFP
• No. Of Pins: 240
• Supply Voltage Range: 4.75V To 5.25V
• Rohs Compliant: Yes
• Family Name: M68xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

System Integration Module (SIM60)
For each address space bit:
V—Valid
MBAR can be read using the following code. Register D0 will contain the value of MBAR.
6-28
4. AS5—mask supervisor data address space (FC3–FC0=0101)
5. AS4—mask Motorola reserved address space (FC3–FC0=0100)
6. AS3—mask user reserved address space (FC3–FC0=0011)
7. AS2—mask user program address space (FC3–FC0=0010)
8. AS1—mask user data address space (FC3–FC0=0001)
9. AS0—mask Motorola reserved address space (FC3–FC0=0000)
The address space bits for 040 type MPU are:
1. AS8—no relevance for 040 cycles
2. AS7—acknowledge access (TT1-TT0=11)
3. AS6—supervisor code access (TT1-TT0=00, TM2-TM0=110)
4. AS5—supervisor data access (TT1-TT0=00, TM2-TM0=101)
5. AS4—MMU table search code access (TT1-TT0=00, TM2-TM0=100)
6. AS3—MMU table search data access (TT1-TT0=00, TM2-TM0=011)
7. AS2—user code access (TT1-TT0=00, TM2-TM0=010)
8. AS1—user data access (TT1-TT0=00, TM2-TM0=001)
9. AS0—data cache push access (TT1-TT0=00, TM2-TM0=000)
This bit indicates when the contents of the MBAR are valid. The base address value is not
used; therefore, all internal module registers are not accessible until the V-bit is set.
1 = Mask this address space from the internal module selection. The bus cycle goes
0 = Decode for the internal module block.
0 = Contents not valid.
1 = Contents valid.
external.
The user should mask off AS7, AS4, AS3 and AS1 to prevent
unwanted access to the QUICC internal dual port RAM (DPR).
For example, AS7 should be masked out so that the IACK cycle
will not cause an access to the DPR.
When working in the CPU enable mode, an access to this regis-
ter does not affect external space since the cycle is not run ex-
ternally.
Freescale Semiconductor, Inc.
For More Information On This Product,
MC68360 USER’S MANUAL
Go to: www.freescale.com
NOTE
NOTE