MC68EN360CAI25L Freescale Semiconductor, MC68EN360CAI25L Datasheet - Page 582

• Manufacturer Part Number: MC68EN360CAI25L
• Description: IC MPU QUICC 25MHZ 240-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MC68000r

Specifications of MC68EN360CAI25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Core Size: 32 Bit
• Cpu Speed: 25MHz
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: FQFP
• No. Of Pins: 240
• Supply Voltage Range: 4.75V To 5.25V
• Rohs Compliant: Yes
• Family Name: M68xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

Serial Communication Controllers (SCCs)
LPB—Loopback Operation
SIP—Sample Input Pins
LCW—Late Collision Window
NIB—Number of Ignored Bits
FDE—Full Duplex Ethernet (Bit 0 of PSMR)
7.10.23.18 ETHERNET RECEIVE BUFFER DESCRIPTOR (RX BD). The Ethernet con-
troller uses the Rx BD to report information about the received data for each buffer. Figure
7-71 shows an Ethernet Rx BD example.
7-258
This parameter determines how soon after RENA assertion that the Ethernet controller
should begin looking for the start frame delimiter. In most situations, the user would select
22 bits.
0 = Normal Operation.
1 = Loopback operation. The channel is configured into internal or external loopback
0 = Normal operation.
1 = After the frame is received, the value on the PB15–PB8 pins is sampled and written
0 = The definition of a late collision is any collision that occurs 64 or more bytes from
1 = The definition of a late collision is any collision that occurs 56 or more bytes from
000 = Begin searching for the SFD 13 bits after the assertion of RENA.
001 = Begin searching for the SFD 14 bits after the assertion of RENA.
010 = Begin searching for the SFD 15 bits after the assertion of RENA.
011 = Begin searching for the SFD 16 bits after the assertion of RENA.
100 = Begin searching for the SFD 21 bits after the assertion of RENA.
101 = Begin searching for the SFD 22 bits after the assertion of RENA.
110 = Begin searching for the SFD 23 bits after the assertion of RENA.
111 = Begin searching for the SFD 24 bits after the assertion of RENA.
0 = Disable full duplex ethernet mode.
1 = Enable full duplex ethernet.
operation as determined by the DIAG bits in the GSMR. For external loopback, the
DIAG bits should be configured for normal operation. For internal loopback, the
DIAG bits should be configured for loopback operation.
to the end of the last receive buffer of the frame. This value is called a tag byte. If
the frame is discarded, the Ethernet:tag byte is also discarded.
the preamble.
the preamble.
When this bit is set to 1 the LPB bit must also be set to 1.
Freescale Semiconductor, Inc.
For More Information On This Product,
MC68360 USER’S MANUAL
Go to: www.freescale.com
NOTE