MC68EN360CAI25L Freescale Semiconductor, MC68EN360CAI25L Datasheet - Page 279

• Manufacturer Part Number: MC68EN360CAI25L
• Description: IC MPU QUICC 25MHZ 240-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MC68000r

Specifications of MC68EN360CAI25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Core Size: 32 Bit
• Cpu Speed: 25MHz
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: FQFP
• No. Of Pins: 240
• Supply Voltage Range: 4.75V To 5.25V
• Rohs Compliant: Yes
• Family Name: M68xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

SW—Software Watchdog Reset
DBF—Double Bus Fault Monitor Reset
Bit 3—Reserved
LOC—Loss of Clock Reset
SRST—Soft Reset
SRSTP—Soft Reset Pin
6.9.3.4 SOFTWARE WATCHDOG INTERRUPT VECTOR REGISTER (SWIV). The SWIV
contains the 8-bit vector that is returned by the SIM60 during an interrupt acknowledge cycle
in response to an interrupt generated by the SWT. This register can be read or written at any
time. This register is set to the uninitialized vector, $0F, at reset.
6.9.3.5 SYSTEM PROTECTION CONTROL REGISTER (SYPCR). The SYPCR controls
the system monitors, the prescaler for the SWT, and the bus monitor timing. This register
can be read at any time, but can be written only once after system reset.
1 = The last reset was caused by the software watchdog circuit.
1 = The last reset was caused by the double bus fault monitor.
1 = The last reset was caused by a loss of frequency reference to the clock sub-mod-
1 = The last reset was caused by the CPU32+ executing a RESET instruction. The RE-
1 = The last reset was caused by an external signal driving RESETS. See Section 3
ule. This reset can only occur if the RSTEN bit in the clock sub-module is set and
the VCO is enabled.
SET instruction does not load a reset vector or affect any internal CPU32+ regis-
ters or SIM60 configuration registers, but does reset external devices and other
internal modules. See Section 3 QUICC Memory Map for a listing of registers af-
fected by the hard reset. This bit is not valid in CPU disable mode.
QUICC Memory Map for a listing of registers affected by the soft reset.
RESET:
RESET:
SWIV7
Freescale Semiconductor, Inc.
SWE
7
0
7
1
For More Information On This Product,
SWIV6
SWRI
6
0
6
1
MC68360 USER’S MANUAL
Go to: www.freescale.com
MODCK
SWIV5
SWT1
5
0
5
1
MODCK
SWIV4
SWT0
4
0
4
1
SWIV3
DBFE
3
1
3
0
SWIV2
BME
2
1
2
0
SUPERVISOR ONLY
SUPERVISOR ONLY
SWIV1
BMT1
System Integration Module (SIM60)
1
1
1
0
SWIV0
BMT0
0
0
1
0