MC68EN360CAI25L Freescale Semiconductor, MC68EN360CAI25L Datasheet - Page 948

• Manufacturer Part Number: MC68EN360CAI25L
• Description: IC MPU QUICC 25MHZ 240-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MC68000r

Specifications of MC68EN360CAI25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Core Size: 32 Bit
• Cpu Speed: 25MHz
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: FQFP
• No. Of Pins: 240
• Supply Voltage Range: 4.75V To 5.25V
• Rohs Compliant: Yes
• Family Name: M68xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

Index
Halt Termination 4-41
Hardware Breakpoint 5-37, 5-39, 5-43, 5-56
Hash Table Algorithm 7-253
HDLC 7-114, 7-116, 7-169, 7-178, A-1
HDLC Address Recognition Example 7-174
HDLC Bus 7-178
HDLC Bus 1-10, 7-189, A-2
INDEX-8
DPLL Error 7-182
FIFO 7-177, 7-179
Flag Status 7-186
Frames Threshold 7-174
Glitch 7-185
HDLC Address Recognition Example 7-
HDLC Channel Frame Reception
HDLC Channel Frame Transmission
HDLC Command Set 7-175
HDLC Controller 7-169
HDLC Error-Handling 7-176
HDLC Example 7-187
HDLC Framing Structure 7-171
HDLC Memory map 7-172
HDLC Programming Model 7-174
HDLC Rx BD 7-180
Idle Sequence Status 7-186
Nonoctet Aligned 7-177
Accessing the HDLC Bus 7-192
Delayed RTS Mode 7-194
GSMR Programming 7-196
HDLC Bus Controller 7-189
HDLC Bus Controller Example 7-196
HDLC Bus Key Features 7-192
HDLC Bus Memory Map and
HDLC Bus Multi-Master Configuration 7-
HDLC Bus Single-Master Configuration
Non-Symmetrical Duty Cycle 7-193
PSMR Programming 7-196
T1.605 7-190
Transmission Line Configuration 7-194
TSA Transmission line Configuration 7-
58
174
Processing 7-172
Processing 7-171
Programming 7-196
191
7-191
195
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HDLC Bus Collision Detection 7-193
HDLC Bus Controller 7-189
HDLC Bus Controller Example 7-196
HDLC Bus Key Features 7-192
HDLC Bus Memory Map and Programming
HDLC Bus Multi-Master Configuration 7-
HDLC Bus Single-Master Configuration 7-
HDLC Channel Frame Reception
HDLC Channel Frame Transmission
HDLC Command Set 7-175
HDLC Controller 7-169
HDLC Error-Handling 7-176
HDLC Example 7-187
HDLC Frames 7-196
HDLC Interrupt 7-185
HDLC Memory Map 7-172
HDLC Programming Model 7-174
HDLC Receive Buffer Descriptor 7-179
HDLC Rx BD 7-180
HDLC Transmit Buffer Descriptor 7-183
Heartbeat 7-257, 7-263
Highest Priority 7-380
HMASK 7-173
I/O Pins 7-333
IACK 2-7, 2-8, 6-48
IACK5 4-39
IADDR 7-250
ICCR 7-26
IDL 7-80, 7-90, 7-268
IDL Interface Example 7-91
IDL Interface Programming 7-95
Idle Sequence Status 7-186
Idle Status 7-167
IDMA 6-31, 7-59
IDMA (Independent DMA Controller
IDMA (Independent DMA Controller) 7-35,
External Cycle Steal 7-42
IDMA Controllers 7-24
Auto Buffer Example 7-56
7-196
191
191
Processing 7-172
Processing 7-171
7-36
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