MC68EN360CAI25L Freescale Semiconductor, MC68EN360CAI25L Datasheet - Page 219

• Manufacturer Part Number: MC68EN360CAI25L
• Description: IC MPU QUICC 25MHZ 240-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MC68000r

Specifications of MC68EN360CAI25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Core Size: 32 Bit
• Cpu Speed: 25MHz
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: FQFP
• No. Of Pins: 240
• Supply Voltage Range: 4.75V To 5.25V
• Rohs Compliant: Yes
• Family Name: M68xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

Operand Data:
Result Data:
5.6.2.8.12 Resume Execution (GO). The pipeline is flushed and refilled before normal
instruction execution is resumed. Prefetching begins at the return PC and current privilege
level. If either the PC or SR is altered during BDM, the updated value of these registers is
used when prefetching commences.
Command Format:
Command Sequence:
Operand Data:
Result Data:
5.6.2.8.13 Call User Code (CALL). This instruction provides a convenient way to patch
user code. The return PC is stacked at the location pointed to by the current SP. The stacked
PC serves as a return address to be restored by the RTS command that terminates the
patch routine. After stacking is complete, the 32-bit operand data is loaded into the PC. The
pipeline is flushed and refilled from the location pointed to by the new PC, BDM is exited,
and normal mode instruction execution begins.
A single operand is data to be written to the memory location. Byte data is transmitted as
a 16-bit word, justified in the least significant byte; 16- and 32-bit operands are transmitted
as 16 and 32 bits, respectively.
Status is returned as in the WRITE command: $0FFFF for a successful operation and
$10001 for a bus or address error during write.
15
None
None
0
14
0
The processor exits BDM when a bus error or address error oc-
curs on the first instruction prefetch from the new PC—the error
is trapped as a normal mode exception. The stacked value of the
current PC may not be valid in this case, depending on the state
of the machine prior to entering BDM. For address error, the PC
does not reflect the true return PC. Instead, the stacked fault ad-
dress is the (odd) return PC.
13
0
12
0
Freescale Semiconductor, Inc.
11
1
For More Information On This Product,
GO
???
10
1
MC68360 USER’S MANUAL
Go to: www.freescale.com
9
0
NOTE
8
0
NORMAL
"ILLEGAL"
MODE
XXX
7
0
6
0
"NOT READY"
NEXT CMD
5
0
4
0
0
3
2
0
1
0
CPU32+
0
0