MC68EN360CAI25L Freescale Semiconductor, MC68EN360CAI25L Datasheet - Page 199

• Manufacturer Part Number: MC68EN360CAI25L
• Description: IC MPU QUICC 25MHZ 240-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MC68000r

Specifications of MC68EN360CAI25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Core Size: 32 Bit
• Cpu Speed: 25MHz
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: FQFP
• No. Of Pins: 240
• Supply Voltage Range: 4.75V To 5.25V
• Rohs Compliant: Yes
• Family Name: M68xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

frames of other M68000 family members. The only internal machine state required in the
CPU32+ stack frame is the bus controller state at the time of the error and a single register.
Bus operation in progress at the time of a fault is conveyed by the SSW.
The bus error stack frame is 12 words in length. There are three variations of the frame, each
distinguished by different values in the SSW TP and MV fields.
An internal transfer count register appears at location SP + $14 in all bus error stack frames.
The register contains an 8-bit microcode revision number and, for type III faults, an 8-bit
transfer count. Register format is shown in Figure 5-14.
The microcode revision number is checked before a bus error stack frame is restored via
RTE. In a multiprocessor system, this check ensures that a processor using stacked infor-
mation is at the same revision level as the processor that created it.
The transfer count is ignored unless the MV bit in the stacked SSW is set. If the MV bit is
set, the least significant byte of the internal register is reloaded into the MOVEM transfer
counter during RTE execution.
For faults occurring during normal instruction execution (both prefetches and non-MOVEM
operand accesses), SSW TP,MV = 00. Stack frame format is shown in Figure 5-15.
Faults that occur during the operand portion of the MOVEM instruction are identified by SSW
TP,MV = 01. Stack frame format is shown in Figure 5-16.
When a bus error occurs during exception processing, SSW TP,MV = 10. The frame shown
in Figure 5-17 is written below the faulting frame. Stacking begins at the address pointed to
by SP – 6 (SP value is the value before initial stacking on the faulted frame).
The frame can have either four or six words, depending on the type of error. Four-word stack
frames do not include the faulted instruction PC. (The internal transfer count register is
located at SP
The fault address of a dynamically sized bus cycle is the address of the upper byte, regard-
less of the byte that caused the error.
TP
15
15
MV
14
SZC1
MICROCODE REVISION NUMBER
13
$10 and the SSW is located at SP
TR
12
Figure 5-14. Internal Transfer Count Register
Freescale Semiconductor, Inc.
11
B1
For More Information On This Product,
B0
10
MC68360 USER’S MANUAL
Go to: www.freescale.com
RR
9
RM
8
8
IN
7
7
$12.)
RW
6
SZC0
5
TRANSFER COUNT
4
SIZ
3
2
FUNC
1
CPU32+
0
0