MC68EN360CAI25L Freescale Semiconductor, MC68EN360CAI25L Datasheet - Page 702

• Manufacturer Part Number: MC68EN360CAI25L
• Description: IC MPU QUICC 25MHZ 240-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MC68000r

Specifications of MC68EN360CAI25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Core Size: 32 Bit
• Cpu Speed: 25MHz
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: FQFP
• No. Of Pins: 240
• Supply Voltage Range: 4.75V To 5.25V
• Rohs Compliant: Yes
• Family Name: M68xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

CPM Interrupt Controller (CPIC)
SCcP—SCCc Priority Order
SCbP—SCCb Priority Order
SCaP—SCCa Priority Order
IRL2–IRL0—Interrupt Request Level
7-378
These two bits define which SCC will assert its request in the SCCc priority position. The
user should not program the same SCC to more than one priority position (a, b, c, or d).
These bits may be changed dynamically.
These two bits define which SCC will assert its request in the SCCb priority position. The
user should not program the same SCC to more than one priority position (a, b, c, or d).
These bits may be changed dynamically.
These two bits define which SCC will assert its request in the SCCa priority position. The
user should not program the same SCC to more than one priority position (a, b, c, or d).
These bits may be changed dynamically.
The IRL field contains the priority request level of the interrupt from the CPM that is sent
to the CPU32+ core. Level 7 indicates a nonmaskable interrupt; level 0 indicates that all
CPM interrupts are disabled. The IRL field, therefore, acts as a master enable for the CPM
interrupts in addition to specifying the interrupt priority level. The IRL field is initialized to
zero during reset to prevent the CPM from generating an interrupt until this register has
been initialized. Value $4 is a good value to choose for the IRL field in most systems.
00 = SCC1 will assert its request in the SCCc position.
01 = SCC2 will assert its request in the SCCc position.
10 = SCC3 will assert its request in the SCCc position.
11 = SCC4 will assert its request in the SCCc position.
00 = SCC1 will assert its request in the SCCb position.
01 = SCC2 will assert its request in the SCCb position.
10 = SCC3 will assert its request in the SCCb position.
11 = SCC4 will assert its request in the SCCb position.
00 = SCC1 will assert its request in the SCCa position.
01 = SCC2 will assert its request in the SCCa position.
10 = SCC3 will assert its request in the SCCa position.
11 = SCC4 will assert its request in the SCCa position.
In systems with multiple QUICCs sharing the same system bus,
assign these bits to a different request level in each QUICC.
If QUICC is in slave mode (CPU32+ disabled), then the external
IRQx pin corresponding to the value programmed in IRL2–IRL0
should not be used. (For example, if IRL2–IRL0 has the value
$5, then IRQ5 on this QUICC should not be used externally.)
This also applies to the programmable interrupt timer and soft-
ware watchdog in the SIM60 of the slave QUICC.
Freescale Semiconductor, Inc.
For More Information On This Product,
MC68360 USER’S MANUAL
Go to: www.freescale.com
NOTES