MC68EN360CAI25L Freescale Semiconductor, MC68EN360CAI25L Datasheet - Page 383

IC MPU QUICC 25MHZ 240-FQFP

MC68EN360CAI25L

Manufacturer Part Number
MC68EN360CAI25L
Description
IC MPU QUICC 25MHZ 240-FQFP
Manufacturer
Freescale Semiconductor
Series
MC68000r

Specifications of MC68EN360CAI25L

Processor Type
M683xx 32-Bit
Speed
25MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
240-FQFP
Core Size
32 Bit
Cpu Speed
25MHz
Embedded Interface Type
SCP, TDM
Digital Ic Case Style
FQFP
No. Of Pins
240
Supply Voltage Range
4.75V To 5.25V
Rohs Compliant
Yes
Family Name
M68xxx
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
25MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
5V
Operating Supply Voltage (max)
5.25V
Operating Supply Voltage (min)
4.75V
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
240
Package Type
FQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC68EN360CAI25L
Manufacturer:
APLHA
Quantity:
12 000
Part Number:
MC68EN360CAI25L
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MC68EN360CAI25L
Manufacturer:
FREESCALE
Quantity:
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The relative priority between the two IDMAs and the SDMA channels is user programmable.
Regardless of system configuration, if the IDMA is a bus master when a higher priority
SDMA channel needs to transfer over the bus, the SDMA will steal cycles from the IDMA
with no arbitration overhead.
When the QUICC is in slave mode (CPU32+ is disabled) the SDMA can steal cycles from
the IDMA with no arbitration overhead. See Section 4 Bus Operation for diagrams of bus
arbitration by an internal master in slave mode.
7.7.2 SDMA Registers
The SDMA channels have one configuration register; otherwise, they are controlled trans-
parently to the user, through the configuration of the SCCs, SMCs, and SPI. The only user-
accessible registers associated with the SDMA are the SDMA configuration register
(SDCR), SDMA address register (SDAR), a read-only register used for diagnostics in case
of an SDMA bus error, and the SDMA status register (SDSR).
7.7.2.1 SDMA CONFIGURATION REGISTER (SDCR). The 16-bit SDCR is used to config-
ure all 14 SDMA channels. It is always readable and writable in the supervisor mode,
although writing the SDCR is not recommended unless the CP is disabled. SDCR is cleared
at reset.
Figure 7-18. SDMA Bus Arbitration (Normal Operation)
(OUTPUT)
(OUTPUT)
(OUTPUT)
NOTES:
DSACKx
(INPUT)
1. The BCLRO signal is only asserted if the SDMA bus arbitration ID is greater than
BGACK
2. The BR, BG, and BGACK signals are not affected by the SDMA bus arbitration
BCLRO
CLKO1
the BCLROID2–BCLROID0 bits in the SIM60 module configuration register.
process if the CPU32+ is enabled.
(I/O)
(I/O)
BR
BG
AS
Freescale Semiconductor, Inc.
S0
For More Information On This Product,
SDMA INTERNALLY
REQUESTS BUS
OTHER CYCLE
S2
MC68360 USER’S MANUAL
Go to: www.freescale.com
S4
S0
NEGATED DURING
FINAL SDMA
BUS CYCLE
SDMA READ
(32 BITS)
S2
S4
S0
OTHER CYCLE
S2
S4
S0
SDMA Channels

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