MC68EN360CAI25L Freescale Semiconductor, MC68EN360CAI25L Datasheet - Page 611

• Manufacturer Part Number: MC68EN360CAI25L
• Description: IC MPU QUICC 25MHZ 240-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MC68000r

Specifications of MC68EN360CAI25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Core Size: 32 Bit
• Cpu Speed: 25MHz
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: FQFP
• No. Of Pins: 240
• Supply Voltage Range: 4.75V To 5.25V
• Rohs Compliant: Yes
• Family Name: M68xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

channel’s Tx BD ring. The CP confirms transmission or indicates error conditions via the
BDs to inform the processor that the buffers have been serviced.
R—Ready
Bits 14, 11, 10, 7–0—Reserved
W—Wrap (Final BD in Table)
I—Interrupt
CM—Continuous Mode
P—Preamble
OFFSET + 0
OFFSET + 2
OFFSET + 4
OFFSET + 6
NOTE : Entries in boldface must be initialized by the user.
0 = The data buffer associated with this BD is not ready for transmission. The user is
1 = The data buffer, which has been prepared for transmission by the user, has not
0 = This is not the last BD in the Tx BD table.
1 = This is the last BD in the Tx BD Table. After this buffer has been used, the CP will
0 = No interrupt is generated after this buffer has been serviced.
1 = The TX bit in the SMC UART event register will be set when this buffer has been
0 = Normal operation.
1 = The R-bit is not cleared by the CP after this BD is closed, allowing the associated
0 = No preamble sequence is sent.
1 = The UART will send one all-ones character before sending the data so that the oth-
free to manipulate this BD or its associated data buffer. The CP clears this bit after
the buffer has been transmitted or after an error condition is encountered.
been transmitted or is currently being transmitted. No fields of this BD may be writ-
ten by the user once this bit is set.
receive incoming data into the first BD in the table (the BD pointed to by TBASE).
The number of Tx BDs in this table is programmable and is determined only by the
W-bit and the overall space constraints of the dual-port RAM.
serviced. TX can cause an interrupt if it is enabled.
data buffer to be retransmitted automatically when the CP next accesses this BD.
er end will detect an idle line before the data is received. If this bit is set and the
data length of this BD is zero, only a preamble will be sent.
15
R
14
—
13
W
Freescale Semiconductor, Inc.
For More Information On This Product,
12
I
11
—
MC68360 USER’S MANUAL
Go to: www.freescale.com
10
—
CM
TX DATA BUFFER POINTER
9
DATA LENGTH
P
8
—
7
Serial Management Controllers (SMCs)
—
6
—
5
—
4
—
3
—
2
—
1
—
0