MC68EN360CAI25L Freescale Semiconductor, MC68EN360CAI25L Datasheet - Page 570

• Manufacturer Part Number: MC68EN360CAI25L
• Description: IC MPU QUICC 25MHZ 240-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MC68000r

Specifications of MC68EN360CAI25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Core Size: 32 Bit
• Cpu Speed: 25MHz
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: FQFP
• No. Of Pins: 240
• Supply Voltage Range: 4.75V To 5.25V
• Rohs Compliant: Yes
• Family Name: M68xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

SDACK2
SDACK1
RRJCT
NOTE: The diagram shows SDMA system bus writes, not data on the RXD pin. Other bus activity may occur between successive
Serial Communication Controllers (SCCs)
7.10.23.8 ETHERNET MEMORY MAP. When configured to operate in Ethernet mode, the
QUICC overlays the structure described in Table 7-5 onto the protocol-specific area of the
SCC parameter RAM described in Table 7-11.
7-246
NOTE: The receive data is sent to the CAM as it is written to system memory. The SDACK2–SDACK1 signals are used to identify the
32-bit writes. In such a case, the SDACK2–1 pins would not be asserted for other bus activity.
WRITES
SDMA
destination address and any other frame bytes desired. The RSTRT signal is not required in this configuration, although
it is still available.
ASSERTED FOR ONE
BUS
16-BIT BUS WRITE
CYCLE OR TWO
CYCLES, ETC.
4 BYTES
ADDR.
DEST.
SYSTEM BUS
Figure 7-69. QUICC Ethernet Parallel CAM Interface
2 BYTES
ADDR.
DEST.
ASSERTED ON EACH
MEMORY UP TO AND
LAST SYSTEM BUS
WRITE CYCLE TO
INCLUDING THE
WRITE OF THE
Freescale Semiconductor, Inc.
FRAME
For More Information On This Product,
6 BYTES
SOURCE
FRAME TAG
OPTIONAL
ADDR.
BYTE
SDACK2–SDACK1
QUICC
SCC
PB15–PB8
MC68360 USER’S MANUAL
PARALLEL I/O
RCLK (CLKx)
TCLK (CLKx)
Go to: www.freescale.com
TENA (RTS)
CLSN (CTS)
RENA (CD)
2 BYTES
LENGTH
RSTRT
TYPE/
RRJCT
TxD
RxD
TRANSMISSIONS ON SYSTEM BUS CEASE,
AND BUFFER DESCRIPTORS ARE REUSED.
FRAME CAN BE REJECTED IF ASSERTED
DURING FRAME RECEPTION. FURTHER
SDACK1 ASSERTED WHEN NEW FRAME
CAM CONTROL
ARRIVES.
46–1500 BYTES
DATA
TX
TENA
TCLK
RX
RENA
RCLK
CLSN
LOOP
MC68160
EEST
CAM
SEQUENCE
4 BYTES
FRAME
CHECK
BYTE COULD BE BYTE 0, 1, 2,
OR 3 OF THE 32-BIT WRITE.
TO MEMORY ONLY IF TAG
BYTE IS APPENDED. TAG
LAST 32-BIT BUS WRITE
;
(OPTIONAL)
TO MEDIA
TAG
SIGNIFIES
1 BYTE