MC68EN360CAI25L Freescale Semiconductor, MC68EN360CAI25L Datasheet - Page 390

• Manufacturer Part Number: MC68EN360CAI25L
• Description: IC MPU QUICC 25MHZ 240-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MC68000r

Specifications of MC68EN360CAI25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Core Size: 32 Bit
• Cpu Speed: 25MHz
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: FQFP
• No. Of Pins: 240
• Supply Voltage Range: 4.75V To 5.25V
• Rohs Compliant: Yes
• Family Name: M68xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

Serial Interface with Time Slot Assigner
The TSA also allows two TDM channels to be supported simultaneously. Thus, in its most
flexible mode, the TSA can provide two separate TDM channels, each with an independent
receive and transmit routing assignment and independent sync pulse and clock inputs (see
Figure 7-21). Thus, the TSA can support four, independent, half-duplex TDM sources, two
in reception and two in transmission, using four sync inputs and four clock inputs.
In addition to channel programming, the TSA supports up to four strobe outputs that may be
asserted on a bit basis or a byte basis. These strobes are completely independent from the
channel routing used by the SCCs and SMCs. They are useful for interfacing to other
devices that do not support the multiplexed interface or for enabling/disabling three-state I/
O buffers in a multi-transmitter architecture. (Note that open-drain programming on the
TXDx pins to support a multi-transmitter architecture is programmed in the parallel I/O
block.) These strobes can also be used for generating output waveforms to support such
applications as stepper motor control.
Most TSA programming is accomplished in two SI RAMs, each of size 64
SI RAMs are directly accessible by the host processor in the internal register section of the
QUICC and are not associated with the dual-port RAM. One SI RAM is always used to pro-
7-66
NOTE: SCCs may receive on one TDM and transmit on another (e.g., SCC2 and SCC3).
QUICC
TSA
TDMa
TDMb
Figure 7-21. Dual TDM Channel Example
Freescale Semiconductor, Inc.
TDMa Tx CLOCK
TDMa Rx CLOCK
TDMb Tx CLOCK
TDMb Rx CLOCK
For More Information On This Product,
TDMb Rx SYNC
TDMa Rx SYNC
TDMa Tx SYNC
TDMb Tx SYNC
TDMa Rx
TDMb Rx
TDMa Tx
TDMb Tx
MC68360 USER’S MANUAL
Go to: www.freescale.com
SCC2
SCC3
SMC1
SCC2
SCC2
SCC4
SCC3
SMC1
16 bits. These