MC68EN360CAI25L Freescale Semiconductor, MC68EN360CAI25L Datasheet - Page 181

• Manufacturer Part Number: MC68EN360CAI25L
• Description: IC MPU QUICC 25MHZ 240-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MC68000r

Specifications of MC68EN360CAI25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Core Size: 32 Bit
• Cpu Speed: 25MHz
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: FQFP
• No. Of Pins: 240
• Supply Voltage Range: 4.75V To 5.25V
• Rohs Compliant: Yes
• Family Name: M68xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

5.5.1.4 MULTIPLE EXCEPTIONS. Each exception has been assigned a priority based on
its relative importance to system operation. Priority assignments are shown in Table 5-17.
Group 0 exceptions have the highest priorities; group 4 exceptions have the lowest priorities.
Exception processing for exceptions that occur simultaneously is done by priority, from high-
est to lowest.
It is important to be aware of the difference between exception processing mode and exe-
cution of an exception handler. Each exception has an assigned vector that points to an
associated handler routine. Exception processing includes steps described in 5.5.1.2
Exception Processing Sequence, but does not include execution of handler routines, which
is done in normal mode.
When the CPU32+ completes exception processing, it is ready to begin either exception
processing for a pending exception or execution of a handler routine. Priority assignment
governs the order in which exception processing occurs, not the order in which exception
handlers are executed.
As a general rule, when simultaneous exceptions occur, the handler routines for lower pri-
ority exceptions are executed before the handler routines for higher priority exceptions. For
example, consider the arrival of an interrupt during execution of a TRAP instruction while
tracing is enabled. Trap exception processing (2) is done first, followed immediately by
exception processing for the trace (4.1), and then by exception processing for the interrupt
(4.3). Each exception places a new context on the stack. When the processor resumes nor-
mal instruction execution, it is vectored to the interrupt handler, which returns to the trace
handler that returns to the trap handler.
There are special cases to which the general rule does not apply. The reset exception will
always be the first exception handled since reset clears all other exceptions. It is also pos-
sible for high-priority exception processing to begin before low-priority exception processing
is complete. For example, if a bus error occurs during trace exception processing, the bus
error will be processed and handled before trace exception processing has completed.
Priority
Group/
1.1
1.2
4.1
4.2
4.3
0
2
3
Reset
Address Error
Bus Error
BKPT#n, CHK, CHK2,
Division by Zero, RTE,
TRAP#n, TRAPcc, TRAPV
Illegal Instruction, Line A,
Unimplemented Line F,
Privilege Violation
Trace
Hardware Breakpoint
Interrupt
Freescale Semiconductor, Inc.
Table 5-17. Exception Priority Groups
For More Information On This Product,
Relative Priority
Exception and
MC68360 USER’S MANUAL
Go to: www.freescale.com
Aborts all processing (instruction or excep-
tion); does not save old context.
Suspends processing (instruction or excep-
tion); saves internal context.
Exception processing is a part of instruction
execution.
Exception processing begins before instruc-
tion execution.
Exception processing begins when current in-
struction or previous exception processing is
complete.
Characteristics
CPU32+