MC68EN360CAI25L Freescale Semiconductor, MC68EN360CAI25L Datasheet - Page 453

• Manufacturer Part Number: MC68EN360CAI25L
• Description: IC MPU QUICC 25MHZ 240-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MC68000r

Specifications of MC68EN360CAI25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Core Size: 32 Bit
• Cpu Speed: 25MHz
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: FQFP
• No. Of Pins: 240
• Supply Voltage Range: 4.75V To 5.25V
• Rohs Compliant: Yes
• Family Name: M68xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

7.10.8.2 SCC MASK REGISTER (SCCM). The 16-bit, read-write SCC mask register allows
the user to either enable or disable interrupt generation by the CP for specific events in each
SCC channel. Note that an interrupt will only be generated if the SCC interrupts in this chan-
nel are enabled in the CPM interrupt mask register.
If a bit in the SCC mask register is zero, the CP will not proceed with its usual interrupt han-
dling whenever that event occurs. Anytime a bit in the SCC mask register is set, a one in the
corresponding bit in the SCC event register will set the SCC event bit in the CPM interrupt
pending register.
The bit position of the SCC mask register is identical to that of the SCC event register.
7.10.8.3 SCC STATUS REGISTER (SCCS). The 8-bit, read-write SCC status register
allows the user to monitor real-time status conditions on the RXD line, such as flags, idle,
and data carrier sense. It does not show the real-time status of the CTS and CD pins. Their
real-time status is available in the port C parallel I/O.
7.10.9 SCC Initialization
The SCCs require a number of registers and parameters to be configured after a power-on
reset. The following outline is the proper sequence for initializing the SCCs, regardless of
the protocol used. More detailed examples are given in the protocol sections.
The BDs may have their ready/empty bits set at any time. Notice that the CR does not need
to be accessed following a power-on reset. An SCC should be disabled and reenabled after
1. Write the parallel I/O ports to configure the I/O pins to connect to the SCCs.
2. The SDCR (SDMA Configuration Register) should be initialized to $0740, rather than
3. Write the port C registers to configure the CTS and CD pins to be parallel I/O with
4. If the TSA is used, the SI must be configured. See 7.8 Serial Interface with Time Slot
5. Write GSMR, but do not write the ENT or ENR bits yet.
6. Write the PSMR.
7. Write DSR.
8. Initialize the required values for this SCC in its parameter RAM.
9. Clear out any current events in the SCCE, if desired.
10. Write SCCM to enable the interrupts in the SCCE.
11. 1Write CICR to configure the SCC’s interrupt priority.
12. 1Clear out any current interrupts in CIPR, if desired.
13. 1Write CIMR to enable interrupts to the CP interrupt controller.
14. 1Set the ENT and ENR bits in the GSMR.
being left at its default value of $0000.
interrupt capability or to be direct connections to the SCC (if modem support is
needed).
Assigner for a description of the steps required. If the SCC is used in
the NMSI mode, then the SICR must still be initialized.
Freescale Semiconductor, Inc.
For More Information On This Product,
MC68360 USER’S MANUAL
Go to: www.freescale.com
Serial Communication Controllers (SCCs)