MC68EN360CAI25L Freescale Semiconductor, MC68EN360CAI25L Datasheet - Page 242

• Manufacturer Part Number: MC68EN360CAI25L
• Description: IC MPU QUICC 25MHZ 240-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MC68000r

Specifications of MC68EN360CAI25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Core Size: 32 Bit
• Cpu Speed: 25MHz
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: FQFP
• No. Of Pins: 240
• Supply Voltage Range: 4.75V To 5.25V
• Rohs Compliant: Yes
• Family Name: M68xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

CPU32+
5.7.2.13 EXCEPTION-RELATED INSTRUCTIONS AND OPERATIONS. The
related instructions and operations table indicates the number of clock periods needed for
the processor to perform the specified exception-related actions. No additional tables are
needed to calculate total effective execution time for these instructions. The total number of
clock cycles is outside the parentheses. The numbers inside parentheses (r/p/w) are
included in the total clock cycle number. All timing data assumes two-clock reads and writes.
5-100
BKPT (Acknowledged)
BKPT (Bus Error)
Breakpoint (Acknowledged)
Breakpoint (Bus Error)
Interrupt
RESET
STOP
LPSTOP
Divide-by-Zero
Trace
TRAP #
ILLEGAL
A-line
F-line (First word illegal)
F-line (Second word illegal) ea = Rn
F-line (Second word illegal) ea
F-line (Second word illegal) ea
Privileged
TRAPcc (trap)
TRAPcc (no trap)
TRAPcc.W (trap)
TRAPcc.W (no trap)
TRAPcc.L (trap)
TRAPcc.L (no trap)
TRAPV (trap)
TRAPV (no trap)
Timing is calculated with the CPU32+ in 16-bit mode.
NOTE: The F-line (second word illegal) operation involves a save step which other
operations do not have. To calculate the total operation time, calculate the save, the calculate
EA, and the operation execution times, and combine in the order
listed, using the equations given in 5.7.1.6 Instruction Execution Time Calculation.
Minimum interrupt acknowledge cycle time is assumed to be three clocks.
Instruction
Freescale Semiconductor, Inc.
For More Information On This Product,
MC68360 USER’S MANUAL
Rn (Save)
Rn (Op)
Go to: www.freescale.com
Head
0
0
0
0
0
0
2
3
0
0
4
0
0
0
1
1
4
0
2
2
2
0
0
0
2
2
Tail
0
0
0
0
1
0
0
0
0
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
518(0/1/0)
30(3/2/4)
14(1/0/0)
35(3/2/4)
10(1/0/0)
42(3/2/6)
12(0/1/0)
25(0/3/1)
36(2/2/6)
36(2/2/6)
29(2/2/4)
25(2/2/4)
25(2/2/4)
25(2/2/4)
31(2/3/4)
29(2/2/4)
25(2/2/4)
38(2/2/6)
38(2/2/6)
38(2/2/6)
38(2/2/6)
3(0/1/0)
4(0/1/0)
4(0/2/0)
6(0/3/0)
4(0/1/0)
Cycles
exception-