MC68EN360CAI25L Freescale Semiconductor, MC68EN360CAI25L Datasheet - Page 362

• Manufacturer Part Number: MC68EN360CAI25L
• Description: IC MPU QUICC 25MHZ 240-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MC68000r

Specifications of MC68EN360CAI25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Core Size: 32 Bit
• Cpu Speed: 25MHz
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: FQFP
• No. Of Pins: 240
• Supply Voltage Range: 4.75V To 5.25V
• Rohs Compliant: Yes
• Family Name: M68xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

IDMA Channels
DE—Destination Access Bus Error
DA—Done Asserted During Transfer
Data Length
Source Buffer Pointer
Destination Buffer Pointer
7.6.4.2.3 IDMA Commands (INIT_IDMA). This command causes the RISC controller to
reinitialize its IDMA internal state to the condition it had after a system reset. The IDMA BD
pointer is reinitialized to the top of BD ring. When in the auto buffer and buffer chaining
modes, the IDMA can be reset by setting the RST bit in the CMR and issuing the INIT_IDMA
command. The INIT_IDMA command should only be executed in conjunction with the set-
ting of the RST bit in the CMR.
7.6.4.3 STARTING THE IDMA. Once the channel has been initialized with all parameters
required for a transfer operation, it is started by setting the STR bit in the CMR. After the
channel has been started, any register that describes the current operation may be read but
not modified (SAPR, DAPR, FCR, or BCR).
Once STR has been set, the channel is active and either accepts operand transfer requests
in external mode or generates requests automatically in internal mode. When the first valid
external request is recognized, the IDMA arbitrates for the bus. The DREQx input is ignored
until STR is set.
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The buffer was closed due to a bus error on the destination access. An interrupt (BED)
will be generated, regardless of the I-bit. The RISC will clear the V-bit of this BD.
The buffer was closed due to the assertion of DONEx. An interrupt (DONE) will be gener-
ated, regardless of the I-bit. The RISC will clear the V-bit of this BD.
The data length is the number of bytes that the IDMA should transfer from/to this BD’s
data buffer. The data length should be programmed to a value greater than zero.
The source buffer pointer contains the address of the associated source data buffer. The
buffer may reside in either internal or external memory.
The destination buffer pointer contains the address of the associated destination data
buffer. The buffer may reside in either internal or external memory.
In single address mode when the source is a device, this field is
ignored. In dual address mode when the source is a device, this
field should contain the device address.
In single address mode when the destination is a device, this
field is ignored. In dual address mode when the destination is a
device, this field should contain the device address.
Freescale Semiconductor, Inc.
For More Information On This Product,
MC68360 USER’S MANUAL
Go to: www.freescale.com
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