MC68EN360CAI25L Freescale Semiconductor, MC68EN360CAI25L Datasheet - Page 507

• Manufacturer Part Number: MC68EN360CAI25L
• Description: IC MPU QUICC 25MHZ 240-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MC68000r

Specifications of MC68EN360CAI25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Core Size: 32 Bit
• Cpu Speed: 25MHz
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: FQFP
• No. Of Pins: 240
• Supply Voltage Range: 4.75V To 5.25V
• Rohs Compliant: Yes
• Family Name: M68xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

Rx Data Buffer Pointer
7.10.17.10 HDLC TRANSMIT BUFFER DESCRIPTOR (TX BD). Data is presented to the
HDLC controller for transmission on an SCC channel by arranging it in buffers referenced
by the channel’s Tx BD table. The HDLC controller confirms transmission (or indicates error
conditions) using the BDs to inform the CPU32+ core that the buffers have been serviced.
R—Ready
Bits 14, 8–2—Reserved
W—Wrap (Final BD in Table)
I—Interrupt
L—Last
The receive buffer pointer, which always points to the first location of the associated data
buffer, may reside in either internal or external memory. The Rx buffer pointer must be
divisible by 4.
OFFSET + 0
OFFSET + 2
OFFSET + 4
OFFSET + 6
NOTE: Entries in boldface must be initialized by the user.
0 = The data buffer associated with this BD is not ready for transmission. The user is
1 = The data buffer, which has been prepared for transmission by the user, has not
0 = This is not the last BD in the Tx BD table.
1 = This is the last BD in the TxBD in the table. After this buffer has been used, the CP
0 = No interrupt is generated after this buffer has been serviced.
1 = Either TXB or TXE in the HDLC event register will be set when this buffer has been
0 = This is not the last buffer in the frame.
1 = This is the last buffer in the current frame.
free to manipulate this BD or its associated data buffer. The CP clears this bit after
the buffer has been transmitted or after an error condition is encountered.
been transmitted or is currently being transmitted. No fields of this BD may be writ-
ten by the user once this bit is set.
will transmit data from the first BD in the table (the BD pointed to by TBASE). The
number of Tx BD s in this table is programmable, and is determined only by the W-
bit and the overall space constraints of the dual-port RAM.
serviced by the HDLC controller. These bits can cause interrupts (if enabled).
15
R
14
—
13
W
Freescale Semiconductor, Inc.
For More Information On This Product,
12
I
MC68360 USER’S MANUAL
11
L
Go to: www.freescale.com
TC
10
CM
TX DATA BUFFER POINTER
9
DATA LENGTH
—
8
—
Serial Communication Controllers (SCCs)
7
—
6
—
5
—
4
—
3
—
2
UN
1
CT
0