MC68EN360CAI25L Freescale Semiconductor, MC68EN360CAI25L Datasheet - Page 528

• Manufacturer Part Number: MC68EN360CAI25L
• Description: IC MPU QUICC 25MHZ 240-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MC68000r

Specifications of MC68EN360CAI25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Core Size: 32 Bit
• Cpu Speed: 25MHz
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: FQFP
• No. Of Pins: 240
• Supply Voltage Range: 4.75V To 5.25V
• Rohs Compliant: Yes
• Family Name: M68xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

Freescale Semiconductor, Inc.
Serial Communication Controllers (SCCs)
BSYNC. This register contains the value of the SYNC to be transmitted in an underrun con-
dition, transmitted as the second byte of a DLE-SYNC pair, and stripped from incoming data
on receive once the receiver has synchronized to the data using the DSR and SYN1–SYN2
pair.
BDLE. This register contains the value to be transmitted as the first byte of a DLE-SYNC
pair and stripped on receive.
CHARACTER1–8. These values represent control characters that may be recognized by
the BISYNC controller.
RCCM. This value is used to mask the comparison of CHARACTER1–8 so that classes of
control characters may be defined. A one enables the bit comparison and a zero masks it.
The CPU32+ core configures each SCC to operate in one of the protocols by the MODE bits
in the GSMR. The SYN1–SYN2 synchronization characters are programmed in the data
synchronization register.
The BISYNC controller uses the same basic data structure as that used in the other modes.
Receive and transmit errors are reported through their respective BDs. The status of the line
is reflected via the port C pins, and a maskable interrupt can be generated upon each status
change.
There are two basic ways of handling the BISYNC channels. First, data may be inspected
on a per-byte basis, with the BISYNC controller interrupting the CPU32+ core upon receipt
of every byte of data. Second, the BISYNC controller may be operated so that software is
only necessary for handling the first two to three bytes of data; subsequent data (until the
end of the block) can be handled by the BISYNC controller without interrupting the CPU32+
core.
7.10.20.5 BISYNC COMMAND SET. The following transmit and receive commands are
issued to the CR.
7.10.20.5.1 Transmit Commands. The following paragraphs describe the BISYNC trans-
mit commands.
STOP TRANSMIT Command . After a hardware or software reset and the enabling of the
channel in the SCC mode register, the channel is in the transmit enable mode and starts
polling the first BD in the table every 64 transmit clocks (immediately if the TOD bit in the
TODR is set).
The STOP TRANSMIT command aborts transmission after a maximum of 64 additional bits
are transmitted, without waiting until the end of the buffer is reached, and the transmit FIFO
is flushed. The TBPTR is not advanced. No new BD is accessed, and no new buffers are
transmitted for this channel. SYNC characters consisting of SYNC-SYNC or DLE-SYNC
pairs (according to the transmitter mode) will be continually transmitted until transmission is
reenabled by issuing the RESTART TRANSMIT command. The STOP TRANSMIT com-
mand may be used when it is necessary to abort transmission and transmit an EOT control
7-204
MC68360 USER’S MANUAL
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