MC68EN360CAI25L Freescale Semiconductor, MC68EN360CAI25L Datasheet - Page 280

• Manufacturer Part Number: MC68EN360CAI25L
• Description: IC MPU QUICC 25MHZ 240-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MC68000r

Specifications of MC68EN360CAI25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Core Size: 32 Bit
• Cpu Speed: 25MHz
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: FQFP
• No. Of Pins: 240
• Supply Voltage Range: 4.75V To 5.25V
• Rohs Compliant: Yes
• Family Name: M68xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

System Integration Module (SIM60)
SWE—Software Watchdog Enable
SWRI—Software Watchdog Reset/Interrupt Select
SWT1–SWT0—Software Watchdog Timing
The SWT timeout period listed in Table 6-4 gives the formula to derive the SWT timeout for
any clock frequency. The timeout periods are listed for various input frequencies. Note that
the input frequency to the SWT is called EXTALDIV in the formulas and is the EXTAL fre-
quency divided by 1 or by 128, depending on the MODCK1–MODCK0 pins.
NOTES:
6-36
SWP SWT1–SWT0 Software Timeout Period
1. Note that a 4.192-MHz oscillator produces the same 32.768 input frequency (the 4.192 MHz is divided by 128 in the
2. Programming for this timeout period must be done after the programming of the PLL. See also 6.9.3.10 PLL Control
This bit should be cleared by software after a system reset to disable the SWT. See
6.3.1.2.4 Software Watchdog Timer (SWT) for more information.
These bits, along with the SWP bit in the PITR, control the divide ratio used to establish
the timeout period for the SWT. The default value (11) yields the maximum timeout period.
The SWT timeout period is given by the following formula:
or
0
0
1
1
0
0
1
1
oscillator circuit).
Register (PLLCR).
0 = SWT is disabled.
1 = SWT is enabled. (This is the default value after system reset.)
0 = SWT causes a level 7 interrupt to the CPU32+.
1 = SWT causes a system reset. (This is the default value after system reset.)
00
01
10
11
00
01
10
11
For more information on reset see 4.7 Reset Operation.
2
2
2
2
2
2
2
2
9
11
13
15
18
20
22
24
/Input frequency
/Input frequency
/Input frequency
/Input frequency
/Input frequency
/Input frequency
/Input frequency
/Input frequency
Freescale Semiconductor, Inc.
For More Information On This Product,
Table 6-4. Deriving SWT Timeout
(EXTALDIV)/(divide count)
MC68360 USER’S MANUAL
Go to: www.freescale.com
2
divide count
EXTALDIV
32.768 kHz
NOTE
15.6 ms
62.5 ms
250 ms
128 s
512 s
32 s
1 s
8 s
1
1
16.677 MHz
251.5 ms
15.7 ms
62.9 ms
128.8 s
3.9 ms
32.2 s
2.0 s
8.0 s
167.7 ms
25 MHz
10.5 ms
41.9 ms
2.6 ms
21.5 s
85.9 s
1.3 s
5.4 s
33.354 MHz
125.7 ms
31.4 ms
1.9 ms
7.9 ms
16.1 s
64.4 s
1.0 s
4.0 s