MC68EN360CAI25L Freescale Semiconductor, MC68EN360CAI25L Datasheet - Page 728

• Manufacturer Part Number: MC68EN360CAI25L
• Description: IC MPU QUICC 25MHZ 240-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MC68000r

Specifications of MC68EN360CAI25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Core Size: 32 Bit
• Cpu Speed: 25MHz
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: FQFP
• No. Of Pins: 240
• Supply Voltage Range: 4.75V To 5.25V
• Rohs Compliant: Yes
• Family Name: M68xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

Applications
EEPROM may be accessed in succession. The CS4 pin should be programmed to respond
to an 8-Kbyte area in this design.
Only one byte should be written at a time. After a write is made, software is responsible for
waiting the appropriate time (e.g., 10 ms) or for performing data polling to see if the newly
written data byte is correct.
9.1.2.6 DRAM SIMM. Figure 9-6 shows the glueless interface to an MCM36100S DRAM
single in-line memory module (SIMM). The RAS1 line should be programmed to respond to
a 4-Mbyte address space.
This particular SIMM also includes parity support, which is supported with the PRTY3–
PRTY0 signals.
This design also uses the RAS1 double-drive capability, whereby the RAS1DD signal is out-
put by the QUICC to increase the effective drive capability of the RAS1 signal.
After power-on reset, the software must wait the required time before accessing the DRAM.
The required eight read cycles must be performed either in software or by waiting for the
refresh controller to perform these accesses.
9-8
WE0
A12–A0
SYSTEM BUS AND
QUICC-GENERATED SIGNALS
OE
D31–D24
CS4
Figure 9-5. Glueless Interface to EEPROM
Freescale Semiconductor, Inc.
For More Information On This Product,
MC68360 USER’S MANUAL
Go to: www.freescale.com
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
CE (Enable)
OE
WE (Write)
EEPROM
PORT SIZE
8K 8
2864
BYTE
A11
A10
A12
A4
A0
A2
A3
A5
A6
A7
A8
A9
A1