MC68EN360CAI25L Freescale Semiconductor, MC68EN360CAI25L Datasheet - Page 334

• Manufacturer Part Number: MC68EN360CAI25L
• Description: IC MPU QUICC 25MHZ 240-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MC68000r

Specifications of MC68EN360CAI25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Core Size: 32 Bit
• Cpu Speed: 25MHz
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: FQFP
• No. Of Pins: 240
• Supply Voltage Range: 4.75V To 5.25V
• Rohs Compliant: Yes
• Family Name: M68xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

Dual-Port RAM
Only the parameters in the parameter RAM and the microcode RAM option require fixed
addresses to be used. The buffer descriptors, buffer data, and scratchpad RAM may be
located in the internal system RAM or in any unused parameter RAM (for instance, in the
available area when a serial channel or sub-block is not being used).
When a microcode from RAM is executed, certain portions of the system RAM are no longer
available. This includes either the first 512-byte block and the last 256-byte block for a small
RAM microcode, and the first two 512-byte blocks and the last 256-byte block for a large
RAM microcode. The third 512-byte block is always available as system RAM.
7.3.1 Buffer Descriptors
The SCCs, SMCs, SPI always use buffer descriptors for controlling data buffers. The buffer
descriptor format of the SCCs, SMCs, and SPI is identical. The buffer descriptor format for
these channels is shown in the following illustration.
If the IDMA is used in the buffer chaining or auto buffer mode, the IDMA channel also uses
buffer descriptors. The buffer descriptors for the IDMA are described in 7.6.1 IDMA Key Fea-
tures;.
7.3.2 Parameter RAM
The CP maintains a section of dual-port RAM called the parameter RAM. This RAM contains
many parameters for the operation of the SCCs, SMCs, SPI, and the IDMA channels. An
overview of the parameter RAM structure is shown in Figure 7-4. The exact definition of the
parameter RAM is contained in each subsection describing a device that uses a parameter
RAM.
7-10
OFFSET + 0
OFFSET + 2
OFFSET + 4
OFFSET + 6
Freescale Semiconductor, Inc.
For More Information On This Product,
MC68360 USER’S MANUAL
Go to: www.freescale.com
HIGH-ORDER DATA BUFFER POINTER
LOW-ORDER DATA BUFFER POINTER
STATUS AND CONTROL
DATA LENGTH
150