MC68EN360CAI25L Freescale Semiconductor, MC68EN360CAI25L Datasheet - Page 733

• Manufacturer Part Number: MC68EN360CAI25L
• Description: IC MPU QUICC 25MHZ 240-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MC68000r

Specifications of MC68EN360CAI25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Core Size: 32 Bit
• Cpu Speed: 25MHz
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: FQFP
• No. Of Pins: 240
• Supply Voltage Range: 4.75V To 5.25V
• Rohs Compliant: Yes
• Family Name: M68xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

9.2 HOW TO TAKE A QUICC SOFTWARE TEST-DRIVE
At first glance, the QUICC has so many features that the proper initialization sequence may
not be immediately obvious. The following paragraphs address the issue by showing the
proper initialization sequence to use when configuring the QUICC in a system after a power-
up reset.
Included is a step-by-step sequence that will allow the user to use and learn each feature of
the QUICC in a methodical way. The sequence is applicable whether the QUICC is in normal
mode (CPU32+ enabled) or slave mode (CPU32+ disabled). Although the sequence is
designed as a first-time test-drive of the QUICC, it is also useful as a general pattern for an
overall QUICC initialization.
Detailed information of a specific QUICC hardware configuration and the actual values that
should be written to registers may be found in 9.1 Minimum System Configuration and 9.4
Using the QUICC MC68040 Companion Mode . Additionally, many examples of initializing
certain peripherals are contained elsewhere in this manual where that peripheral is
described.
Step 1: Decide on Reset Stack Pointer and Initial Program Counter
CS0 will function after reset and allow code execution from the boot EPROM-type device.
The stack pointer and the reset vector will be read from the first locations of the EPROM,
and the program will execute from EPROM at the initial program counter address offset in
the EPROM. Although the stack pointer is initialized, it is not ready to be used because it
does not yet point to RAM.
Step 2: Stay in Supervisor Mode
After a reset, M68000 family CPUs are in supervisor mode. Program accesses are issued
with the supervisor program function code, and data accesses are issued with the supervi-
sor data function code. These function codes are required for some of the operations that
• To configure the QUICC for 16-bit data bus mode, the system RESET signal should be
• All port sizes should be configured to either 8 or 16 bits. The DRAM port size must be
• Only the D31–D16 pins should be connected to the system bus. Only PRTY0 and
• Only the upper word of the static RAM array should be used. The CS3 line should be
• The DRAM SIMM should be replaced with a 16- or 18-bit-wide version. The RAS1 line
• Only the upper 256K
connected to the PRTY3 pin. In 16-bit data bus mode, the PRTY2 and PRTY3 pins are
not used.
16-bits if internal address multiplexing is used.
PRTY1 should be used. The unused data and parity pins should be pulled high or low
through a resistor to save power and to avoid floating inputs.
programmed to respond to a 64-Kbyte address space.
should be programmed to respond to a 2-Mbyte address space.
programmed to respond to a 512-Kbyte address space.
Freescale Semiconductor, Inc.
For More Information On This Product,
16 bit DRAM device should be used. The RAS1 line should be
MC68360 USER’S MANUAL
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