MC68EN360CAI25L Freescale Semiconductor, MC68EN360CAI25L Datasheet - Page 87

• Manufacturer Part Number: MC68EN360CAI25L
• Description: IC MPU QUICC 25MHZ 240-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MC68000r

Specifications of MC68EN360CAI25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Core Size: 32 Bit
• Cpu Speed: 25MHz
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: FQFP
• No. Of Pins: 240
• Supply Voltage Range: 4.75V To 5.25V
• Rohs Compliant: Yes
• Family Name: M68xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

Figure 4-6 shows a word transfer to an 8-bit bus port. Like the preceding example, this
example requires two bus cycles. Each bus cycle transfers a single byte. The size signals
for the first cycle specify two bytes; for the second cycle, they specify one byte. Figure 4-7
shows the associated bus transfer signal timing.
4.2.2 Misaligned Operands
Since operands may reside at any byte boundaries, they may be misaligned. A byte operand
is properly aligned at any address; a word operand is misaligned at an odd address; a long
word is misaligned at an address that is not evenly divisible by four. The MC68302,
MC68000/MC68008, MC68010, and MC68340 implementations allow long-word transfers
on odd-word boundaries but force exceptions if word or long-word operand transfers are
attempted at odd-byte addresses. Although the QUICC does not enforce any alignment
restrictions for data operands (including PC relative data addresses), some performance
degradation occurs when additional bus cycles are required for long-word or word operands
Figure 4-5. Long-Word Operand Write Timing (16-Bit Data Port)
FC3–FC0
D23–D16
D31–D24
DSACK0
DSACK1
A31–A2
CLKO1
SIZ0
SIZ1
R/W
AS
DS
A0
A1
Freescale Semiconductor, Inc.
For More Information On This Product,
S0
MC68360 USER’S MANUAL
Go to: www.freescale.com
WORD WRITE
S2
LONG-WORD OPERAND WRITE TO 16-BIT PORT
0P0
0P1
S4
S0
WORD WRITE
S2
0P3
0P2
S4
Bus Operation