CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet
CP80617004119AES LBU3
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CP80617004119AES LBU3 Summary of contents
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... Intel® Core™ i7-600, i5-500, i5-400 and i3-300 Mobile Processor Series Datasheet — Volume Two This is volume Refer to Document Number 322812 for Volume 1 November 2010 Document Number: 322813-002 ...
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... Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. 64-bit computing on Intel architecture requires a computer system with a processor, chipset, BIOS, operating system, device drivers and applications enabled for Intel® ...
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Contents 1 Processor Configuration Registers ........................................................................... 12 1.1 Register Terminology ......................................................................................... 12 1.2 System Address Map.......................................................................................... 14 1.2.1 Legacy Address Range ............................................................................ 17 1.2.2 Main Memory Address Range ( TOLUD) ............................................ 19 1.2.3 Main Memory Address Space (4 ...
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PBFC - Primary Buffer Flush Control ..........................................................73 1.8.27 SBFC - Secondary Buffer Flush Control ......................................................73 1.8.28 ERRSTS - Error Status .............................................................................74 1.8.29 ERRCMD - Error Command.......................................................................75 1.8.30 SMICMD - SMI Command.........................................................................76 1.8.31 SCICMD - SCI Command .........................................................................77 1.8.32 SKPD ...
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HWTHROTCTRL1 - Hardware Throttle Control 1 ........................................ 122 1.10.9 TIS1 - Thermal Interrupt Status 1 .......................................................... 123 1.10.10TERATE - Thermometer Mode Enable and Rate ......................................... 125 1.10.11TERRCMD - Thermal Error Command ...................................................... 127 1.10.12TSMICMD - Thermal SMI Command ........................................................ ...
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Prefetchable Memory Limit Address ........................................ 164 1.13.19PMBASEU1 - Prefetchable Memory Base Address Upper.............................. 165 1.13.20PMLIMITU1 - Prefetchable Memory Limit Address Upper ............................. 165 1.13.21CAPPTR1 - Capabilities Pointer................................................................ 166 1.13.22INTRLINE1 - Interrupt Line .................................................................... 167 1.13.23INTRPIN1 - Interrupt Pin........................................................................ ...
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... Interrupt Line ...................................................................... 236 1.16.18INTRPIN - Interrupt Pin ......................................................................... 236 1.16.19MINGNT - Minimum Grant ..................................................................... 236 1.16.20MAXLAT - Maximum Latency .................................................................. 237 1.16.21GGCTL - Graphics Enhanced Intel® SpeedStep Technology Capability ......... 237 1.16.22MGGC - Processor Graphics Control Register ............................................ 239 1.16.23DEVEN - Device Enable ......................................................................... 241 1.16.24SSRW - Software Scratch Read Write ...................................................... 242 1 ...
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... Invalidate Address Register .................................................... 288 1.18.29IOTLB_REG - IOTLB Invalidate Register ................................................... 290 1.18.30FRCD_REG - Fault Recording Registers .................................................... 293 1.18.31VTCMPLRESR - VT-d Completion Resource Dedication ................................ 294 1.18.32VTFTCHARBCTL - VC0/VCp Intel VT-d Fetch Arbiter Control ........................ 297 1.18.33PEGVTCMPLRESR - PEG VT-d Completion Resource Dedication .................... 298 1.19 DMI VC1 REMAP Registers ................................................................................ 300 1 ...
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... IOTLB Invalidate Register ................................................... 382 1.20.30FRCD_REG - Fault Recording Registers .................................................... 384 1.21 Intel® Trusted Execution Technology (Intel® TXT) Specific Registers..................... 386 1.21.1 TXT.DID - TXT Device ID Register........................................................... 386 1.21.2 TXT.DPR - DMA Protected Range ............................................................ 387 1.21.3 TXT.PUBLIC.KEY.LOWER - TXT Processor Public Key Hash Lower Half .......... 388 1 ...
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Figures Figure 1 System Address Range ............................................................................16 Figure 2 Microsoft MS-DOS* Legacy Address Range .................................................17 Figure 3 Main Memory Address Range....................................................................20 Figure 4 PCI Memory Address Range .....................................................................25 Figure 5 Less Than Physical Memory (No Remap) .........................................29 ...
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Revision History Revision Number 001 • Initial Release 002 • Updated Figure 8 for better clarification Datasheet Description § Revision Date January 2010 November 2010 11 ...
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... Processor Configuration Registers This is volume 2 of the Intel Core i7-600, i5-500, i5-400 and i3-300 Mobile Processor Series Datasheet. Throughout this document, the Intel Core i7-600, i5-500, i5-400 and i3-300 Mobile Processor Series may be referred to as simply the processor. This document provides register information for the processor. ...
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Processor Configuration Registers Item RW1C-L-S Read/Write 1 to Clear/Lockable/Sticky bit(s). These bits can be read. Internal events may set this bit. A software write of 1 clears (sets to 0) the corresponding bit(s) and a write of 0 has no ...
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... SMM CSEG/TSEG, PCIexBAR, and DRAM accesses will occur within the CPU and the GMCH has no direct knowledge. In addition, the Intel® Management Engine (Intel® ME) will move to the PCH, so Intel ME associated register ranges have been removed from the Graphics Controller. This section focuses on how the memory space is partitioned and what the separate memory regions are used for ...
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Processor Configuration Registers When running in internal graphics mode, tileX/tileY/linear reads/writes to GMADR range are supported. Write accesses to GMADR linear regions are supported from both DMI and PEG. GMADR write accesses to tileX and tileY regions (defined via fence ...
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Figure 1. System Address Range 16 Processor Configuration Registers Datasheet ...
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Processor Configuration Registers 1.2.1 Legacy Address Range This area is divided into the following address regions: • 0 – 640 KB – Microsoft MS-DOS* Area • 640 – 768 KB – Legacy Video Buffer Area • 768 – 896 KB ...
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DOS Range (0000_0000h – 0009_FFFFh) The DOS area is 640 KB (0000_0000h – 0009_FFFFh) in size and is always mapped to the main memory controlled by the GMCH. 1.2.1.2 Legacy Video Area (000A_0000h-000B_FFFFh) The legacy 128-KB VGA memory range, ...
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Processor Configuration Registers 1.2.1.3 PAM (000C_0000h-000F_FFFFh) The 13 sections from 768 comprise what is also known as the PAM Memory Area. Each section has Read enable and Write enable attributes. The CPU documentation will now contain ...
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Figure 3. Main Memory Address Range FFFF_FFFFh Contains: Dev BARS & ICH/PCI ranges 00F0_0000h 1.2.2.1 ISA Hole (15 MB-16 MB) This register moved to the CPU. As such, the CPU performs the necessary decode and ...
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... Support for protected memory region is required for DMA-remapping hardware implementations on platforms supporting Intel® Trusted Execution Technology (Intel® TxT), and is optional for non-Intel® Virtualization Technology (Intel® VT) for Directed I/O (Intel® VT-d) platforms ...
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... Global GTT Stolen Space (GGSM) GGSM always exists regardless of Intel VT-d as long as internal GFX is enabled. This space is allocated to store accesses as page table entries are getting updated through virtual GTTMMADR range. Hardware is responsible to map PTEs into this physical space. ...
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... Host address map. Intel ME stolen memory base is calculated by subtracting the amount of memory stolen by the Manageability Engine from TOM. Note: Only Intel ME can access this space not accessible by or coherent with any CPU side accesses. 1.2.2.8 PCI Memory Address Range (TOLUD - 4 GB) This address range, from the top of low usable DRAM (TOLUD normally mapped to the DMI Interface ...
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... Addresses decoded to the memory mapped window to PEG/DMI/Intel ME VC0 Intel VT-d remap engine registers (VTDPVC0BAR) 4. TCm accesses (to Intel ME stolen memory) from PCH do not go through Intel VT-d remap engines. Some of the MMIO Bars may be mapped to this range or to the range above TOUUD. ...
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Processor Configuration Registers Figure 4. PCI Memory Address Range FFFF_FFFFh FFE0_0000h FEF0_0000h FEE0_0000h FED0_0000h FEC8_0000h FEC0_0000h F000_0000h E000_0000h Datasheet 4GB High BIOS 4GB - 2MB DMI Interface (subtractive decode) 4GB - 17MB MSI Interrupts 4GB - 18MB DMI Interface (subtractive ...
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APIC Configuration Space (FEC0_0000h-FECF_FFFFh) This range is reserved for APIC configuration space. The I/O APIC(s) usually reside in the PCH portion of the chip-set, but may also exist as stand-alone components like PXH. The IOAPIC spaces are used to ...
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... IO above TOM). Intel ME stolen size register reflects the total amount of physical memory stolen by the Manageability Engine. Intel ME stolen memory is located at the top of physical memory. Intel ME stolen memory base is calculated by subtracting the amount of memory stolen by the Manageability Engine from TOM ...
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... Bottom of physical remap memory defined by the existing TOLUD register. • Top of physical remap memory, which is implicitly defined by either TOM minus Manageability Engine stolen size. Determine the following Mapping steps: 1. TOM 2. TOM minus Intel ME stolen size 3. MMIO allocation 4. TOLUD 5. GFX stolen base 6. GFX GTT stolen base 7. TSEG base 8 ...
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... Address Space allocated to memory mapped • Remapped Physical Memory = 0 GB • TOM – 020h (2 GB) • Intel ME stolen size – 00001b (1 MB) • TOUUD – 07FFh (2 GB minus 1 MB aligned) • TOLUD – 01F00h (2GB minus 64 MB) • REMAPBASE – 3FFh (64 GB – 1 boundary, default) • ...
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... Example Physical Memory, with 1 GB allocated to Memory Mapped IO: • Populated Physical Memory = 5 GB • Address Space allocated to memory mapped • Remapped Physical Memory = 1G B • TOM – 050h (5 GB) • Intel ME stolen size – 00000b (0 MB) 30 HOST/SYSTEM VIEW 64G HMMIO MEMORY RECLAIM REGION DRAM ABOVE ...
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... TOUUD BASE RECLAIM BASE + x In this case the amount of memory remapped is the range between TOLUD and TOM minus the Intel ME stolen memory. This physical memory is mapped to the logical address range defined between the REMAPBASE and the REMAPLIMIT registers. Datasheet HOST/SYSTEM VIEW ...
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... Remapped Physical Memory = 1 GB • TOM – 030h (3 GB) • Intel ME stolen size – 00000b (0 MB) • TOUUD – 1400h (5 GB) (1-MB aligned) • TOLUD – 02000h (2 GB) (64-MB aligned because remap is enabled and the remap register has 64MB granularity) • ...
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... Populated Physical Memory = 5 GB • Address Space allocated to memory mapped • Remapped Physical Memory = 1 GB • TOM – 050h (5 GB) • Intel ME stolen size – 00000b (0 MB) • TOUUD – 17FFh (6GB-1 MB aligned) Datasheet HOST/SYSTEM VIEW 64 GB HMMIO MEMORY 64 MB aligned ...
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TOLUD – 06000h (3 GB) (64 MB aligned because remap is enabled and the remap register has 64MB granularity) • REMAPBASE – 050h (5 GB) • REMAPLIMIT – 05Fh (6 GB – 1 boundary) 1.2.4 PCI Express* Configuration Address ...
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Processor Configuration Registers Note that the GMCH memory range registers described above are used to allocate memory address space for any PCI Express devices sitting on PCI Express that require such a window. The PCICMD1 register can override the routing ...
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IOBAR Mapped Access to Device 2 MMIO Space Device 2, integrated graphics device, contains an IOBAR register. If Device 2 is enabled, then IGD registers or the GTT table can be accessed using this IOBAR. The IOBAR is composed ...
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Processor Configuration Registers 1.2.8 SMM and VGA Access through GTT TLB Accesses through GTT TLB address translation SMM DRAM space are not allowed. Writes is routed to Memory address 000C_0000h with byte enables de-asserted and reads is routed to Memory ...
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The I/O accesses are forwarded normally to the DMI Interface bus unless they fall within the PCI Express I/O address range as defined by the mechanisms explained below. I/O writes are NOT posted. Memory writes to PCH or PCI Express ...
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... PCI Bus 0. Note: A physical PCI bus 0 does not exist. DMI and the internal devices in the processor and Intel PCH logically constitute PCI Bus 0 to configuration software. This is shown in the following figure. The processor contains three PCI devices within a single physical component. The configuration registers for the three devices are mapped as devices residing on PCI Bus 0 ...
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Configuration Mechanisms The processor is the originator of configuration cycles. Internal to the processor transactions received through both configuration mechanisms are translated to the same format. 1.4.1 Standard PCI Configuration Mechanism The following is the mechanism for translating processor ...
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Processor Configuration Registers accessed. Locked transactions to the PCI Express memory mapped configuration address space are not supported. All changes made using either access mechanism are equivalent. The PCI Express Enhanced Configuration Mechanism utilizes a flat memory-mapped address space to ...
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To access this space (step 1 is done only once by BIOS): 1. Write to CSR address 0x01050 to enable the PCI Express enhanced configuration mechanism by writing 1 to Bit 0 of the GQ1_CR_PCIEXBAR register. Allocate either 256, 128, ...
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Processor Configuration Registers Figure 10. Processor Configuration Cycle Flow Chart Pro ce sso Typ e 1 Acce Exp vice # = Pro ...
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Bridge Related Configuration Accesses Configuration accesses on PCI Express or DMI are PCI Express Configuration TLPs. • Bus Number [7:0] is Header Byte 8 [7:0] • Device Number [4:0] is Header Byte 9 [7:3] • Function Number [2:0] is ...
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Processor Configuration Registers If the Bus Number is zero, the processor will generate a Type 0 Configuration Cycle TLP on DMI. If the Bus Number is non-zero, and falls outside the range claimed by the Host-PCI Express bridge, the processor ...
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... When a Reserved register location is read, a zero value is returned. (Reserved registers can bits in size). Writes to Reserved registers have no effect on the processor. Registers that are marked as Intel Reserved must not be modified by system software. Writes to Intel Reserved registers may cause system failure ...
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Processor Configuration Registers Table 3. Device 0 Function 0 Register Summary (Sheet Register Name Vendor Identification Device Identification PCI Command PCI Status Revision Identification Class Code Master Latency Timer Header Type Subsystem Vendor Identification Subsystem Identification Capabilities ...
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... SKPD DC CAPID0 E0 0/0/0/PCI 0-1h 8086h RO 16 bits Default Value 8086h Vendor Identification Number (VID) PCI standard identification for Intel. 0/0/0/PCI 2-3h 0044h RO 16 bits Default Value 0044h Device Identification Number (DID) Identifier assigned to the processor core/primary PCI device. Processor Configuration Registers ...
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Processor Configuration Registers 1.8.3 PCICMD - PCI Command B/D/F/Type: Address Offset: Default Value: Access: Size: Since processor Device 0 does not physically reside on PCI_A many of the bits are not implemented. Bit Access 15: ...
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Bit Access Processor Configuration Registers (Sheet Default Description Value 0b Parity Error Enable (PERRE) Controls whether or not the Master Data Parity ...
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Processor Configuration Registers 1.8.4 PCISTS - PCI Status B/D/F/Type: Address Offset: Default Value: Access: Size: This status register reports the occurrence of error events on Device 0's PCI interface. Since the processor Device 0 does not physically reside on PCI_A ...
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... Stepping Revision ID (SRID) This register contains the revision number of the CPU. The SRID is a 8-bit hardwired value assigned by Intel, based on product’s stepping. The SRID is not a directly addressable PCI register. The SRID value is reflected through the RID register when appropriately addressed. ...
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... Processor Configuration Registers Compatible Revision ID (CRID) The CRID is an 8-bit hardwired value assigned by Intel during manufacturing process. Normally, the value assigned as the CRID will be identical to the SRID value of a previous stepping of the product with which the new product is deemed “compatible”. ...
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MLT - Master Latency Timer B/D/F/Type: Address Offset: Default Value: Access: Size: Device 0 in the processor is not a PCI master. Therefore this register is not implemented. Bit Access 7:0 RO 1.8.8 HDR - Header Type B/D/F/Type: Address ...
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Processor Configuration Registers 1.8.10 SID - Subsystem Identification B/D/F/Type: Address Offset: Default Value: Access: Size: This value is used to identify a particular subsystem. Bit Access 15:0 RW-O 1.8.11 CAPPTR - Capabilities Pointer B/D/F/Type: Address Offset: Default Value: Access: Size: ...
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... PCI 3.0-compliant memory mapped space. On reset, the EGRESS port MMIO configuration space is disabled and must be enabled by writing PXPEPBAREN [Dev 0, Offset 40h, Bit 0]. All the bits in this register are locked in Intel TXT mode. Bit Access ...
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... The register space contains memory control, initialization, timing, and buffer strength registers; clocking registers; and power and thermal management registers. The 16KB space reserved by the MCHBAR register is not accessible during Intel TXT mode of operation or if the Intel® Management Engine (Intel® ME) security lock is asserted (MESMLCK ...
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... Bit Access 0 RW-L 1.8.14 GGC - Processor Graphics Control Register B/D/F/Type: Address Offset: Default Value: Access: Size: All the bits in this register are Intel TXT lockable. Bit Access 15: Processor Configuration Registers (Sheet Default Description Value 0b MCHBAR Enable (MCHBAREN MCHBAR is disabled and does not claim any memory ...
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... No Intel® Virtualization Technology (Intel® VT-d) mode memory pre-allocated for GTT. 3h: No Intel VT-d mode memory pre-allocated for GTT. 9h: Intel VT-d mode memory pre-allocated for Global GTT and 1 MB for Shadow GTT. Ah: Intel VT-d mode memory pre-allocated for 1 Global GTT and 1.5 MB for Shadow GTT. ...
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... Eh-Fh: Reserved. Note:This register is locked and becomes Read Only when the D_LCK bit in the SMRAM register is set. This register is also Intel VT-d lockable. Hardware does not clear or set any of these bits automatically based on IGD being disabled/enabled. BIOS Requirement: BIOS must not set this field IVD (Bit 1 of this register ...
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... IO), and the Sub- Class Code field within Device 2 function 0 Class Code register is 80. BIOS Requirement: BIOS must not set this bit the GMS field (Bits 6:4 of this register) pre-allocates no memory. This bit MUST be set Device 2 is disabled via register (DEVEN[3] = 0). This register is locked by Intel VT-d. Encoding Description ...
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... BIOS Optimal Default Allows for enabling/disabling of PCI devices and functions that are within the processor. The table below the bit definitions describes the behavior of all combinations of transactions to devices controlled by this register. All the bits in this register are Intel TXT Lockable. Bit ...
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... The 4-KB reserved by this register does not alias to any PCI 3.0-compliant memory mapped space. On reset, the Root Complex configuration space is disabled and must be enabled by writing DMIBAREN [Device 0, Offset 68h, Bit 0] All the bits in this register are locked in Intel TXT mode. Bit Access ...
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LAC - Legacy Access Control B/D/F/Type: Address Offset: Default Value: Access: Size: BIOS Optimal Default This 8-bit register controls steering of MDA cycles. There can only be at most one MDA device in the system. BIOS must not program ...
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Processor Configuration Registers Bit Access 0 RW Datasheet (Sheet Default Description Value PEG0 MDA Present (MDAP0) This bit works with the VGA Enable bits in the BCTRL register of Device 1 to control the routing of CPU ...
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... F. Thus the top of the defined range is one byte less than a 64-MB boundary. When the value in this register is less than the value programmed into the Remap Base register, the Remap window is disabled. These Bits are Intel VT-d lockable or Intel ME stolen Memory lockable. Processor Configuration Registers Description Description ...
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... IO). These bits correspond to address Bits 35:26 (64-MB granularity). Bits 25:0 are assumed All the bits in this register are locked in Intel VT-d mode. MCH determines the base of EP stolen memory by subtracting the EP stolen memory size from TOM. ...
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... Address Bits 19:0 are assumed to be 000_0000h for the purposes of address comparison. The Host interface positively decodes an address towards DRAM if the incoming address is less than the value programmed in this register and greater than 4 GB. All the bits in this register are locked in Intel VT-d mode. Processor Configuration Registers Description Datasheet ...
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Processor Configuration Registers 1.8.22 GBSM - Graphics Base of Stolen Memory B/D/F/Type: Address Offset: Default Value: Access: Size: This register contains the base address of graphics data stolen DRAM memory. BIOS determines the base of graphics data stolen memory by ...
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BGSM - Base of GTT Stolen Memory B/D/F/Type: Address Offset: Default Value: Access: Size: This register contains the base address of graphics data stolen DRAM memory. BIOS determines the base of graphics data stolen memory by subtracting the graphics ...
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... GTT Graphics Stolen Memory Size set • BIOS knows the OS requires PCI space. • BIOS also knows the range from 0_FEC0_0000h to 0_FFFF_FFFFh is not usable by the system. This 20-MB range at the very top of addressable memory space is lost to APIC and Intel TXT. Datasheet 0/0/0/PCI AC-AFh 00000000h RO; RW-L ...
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... MB. Configuration software must set this value to the smaller of the following two choices: Maximum amount memory in the system minus Intel ME stolen memory plus one byte or the minimum address allocated for PCI memory. Address Bits 19:0 are assumed to be 0_0000h for the purposes of address comparison. The Host interface positively decodes an address towards DRAM if the incoming address is less than the value programmed in this register ...
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Processor Configuration Registers 1.8.26 PBFC - Primary Buffer Flush Control B/D/F/Type: Address Offset: Default Value: Access: Size: Bit Access 31 1.8.27 SBFC - Secondary Buffer Flush Control B/D/F/Type: Address Offset: Default Value: Access: Size: Bit Access 31:1 ...
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ERRSTS - Error Status B/D/F/Type: Address Offset: Default Value: Access: Size: BIOS Optimal Default This register is used to report various error conditions via the SERR DMI messaging mechanism. An SERR DMI message is generated on a zero to ...
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Processor Configuration Registers 1.8.29 ERRCMD - Error Command B/D/F/Type: Address Offset: Default Value: Access: Size: This register controls the memory controller responses to various system errors. Since the processor does not have an SERRB signal, SERR messages are passed from ...
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SMICMD - SMI Command B/D/F/Type: Address Offset: Default Value: Access: Size: This register enables various errors to generate an SMI DMI special cycle. When an error flag is set in the ERRSTS register, it can generate an SERR, SMI, ...
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Processor Configuration Registers 1.8.31 SCICMD - SCI Command B/D/F/Type: Address Offset: Default Value: Access: Size: This register enables various errors to generate an SMI DMI special cycle. When an error flag is set in the ERRSTS register, it can generate ...
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CAPID0 - Capability Identifier B/D/F/Type: Address Offset: Default Value: Access: Size: Control of bits in this register are for capability SKU differentiation. Bit Access 95:0 RO 1.9 Device 0 MCHBAR DRAM Controls Table 4. Device 0 MCHBAR DRAM Controls ...
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Processor Configuration Registers Table 4. Device 0 MCHBAR DRAM Controls Summary (Sheet Register Register Name Symbol Channel 0 CKE Control C0CKECTRL Channel 0 ODT Control C0ODTCTRL Channel 0 DRAM C0DTC Throttling Control Channel 0 DRAM Rank C0DTPEW ...
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... Reserved 0000h 2 Channel Size (2CHSZ) This register indicates the total memory which is mapped to 2-channel operation (1-MB granularity) This register is locked by Intel ME stolen Memory lock and may also be forced to 0000h by the Performance Dual Channel Disable fuse. 0000h 1 Channel Size (1CHSZ) This register indicates the total memory which is mapped to 1-channel operation (1-MB granularity) This register is locked by Intel ME stolen Memory lock ...
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... Enabled for Bank Selects and Rank Selects 01:XOR Enabled for Bank Selects and Rank Selects 10:Swap Enabled for Bank Selects only 11:XOR Enabled for Bank Select only This register is locked by Intel ME stolen Memory lock. Encoding 00b Swap Enabled for Bank Selects and ...
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... DRAM memory. An added restriction is that the number of ranks/channel has Note: If any of the two channels is in enhanced mode, the other channel should also be in enhanced mode. This register is locked by Intel ME stolen Memory lock. Encoding 0b Standard addressing 1b Enhanced addressing ...
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... Channel 0 DRAM Rank Boundary Address 0 (C0DRBA0) This register defines the DRAM rank boundary for Rank 0 of Channel 0 (64-MB granularity Total Rank 0 memory size/ Total Rank 1 memory size/ Total Rank 2 memory size/ Total Rank 3 memory size/64 MB This register is locked by Intel ME stolen Memory lock. 83 ...
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... Channel 0 DRAM Rank Boundary Address 2 (C0DRBA2) This register defines the DRAM rank boundary for Rank 2 of Channel 0 (64-MB granularity Total Rank 0 memory size/ Total Rank 1 memory size/ Total Rank 2 memory size/ Total Rank 3 memory size/64 MB This register is locked by Intel ME stolen Memory lock. Description Datasheet ...
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... This register defines the DRAM rank boundary for Rank 3 of Channel 0 (64 MB granularity Total Rank 0 memory size/ Total Rank 1 memory size/ Total Rank 2 memory size/ Total Rank 3 memory size/64 MB This register is locked by Intel ME stolen Memory lock. 0/0/0/MCHBAR 208-209h 0000h RW-L 16 bits ...
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... This register is locked by Intel ME stolen Memory lock. 00h Channel 0 DRAM Rank-0 Attributes (C0DRA0) This register defines DRAM page size/number-of-banks for Rank 0 for given channel. See table in register description for programming. This register is locked by Intel ME stolen Memory lock. Processor Configuration Registers Rank Page Capa Size ...
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... See table in register description for programming. This register is locked by Intel ME stolen Memory lock. 00h Channel 0 DRAM Rank-2 Attributes (C0DRA2) This register defines DRAM pagesize/number-of-banks for Rank 2 for given channel. See table in register description for programming. This register is locked by Intel ME stolen Memory lock. 87 ...
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C0CYCTRKPCHG - Channel 0 CYCTRK PCHG B/D/F/Type: Address Offset: Default Value: Access: Size: Channel 0 CYCTRK Precharge Registers. Bit Access 15:11 RO 10:6 RW 5 Processor Configuration Registers 0/0/0/MCHBAR 250-251h 0000h RO bits ...
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Processor Configuration Registers 1.9.10 C0CYCTRKACT - Channel 0 CYCTRK ACT B/D/F/Type: Address Offset: Default Value: Access: Size: Channel 0 CYCTRK Activate Registers. Bit Access 31:28 RO 27: 20:17 RW 16:13 RW 12:9 RW 8:0 RW Datasheet 0/0/0/MCHBAR ...
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C0CYCTRKWR - Channel 0 CYCTRK WR B/D/F/Type: Address Offset: Default Value: Access: Size: Channel 0 CYCTRK WR Registers. Bit Access 15:12 RW 11:8 RW 7 Processor Configuration Registers 0/0/0/MCHBAR 256-257h 0000h RW 16 bits Default ...
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Processor Configuration Registers 1.9.12 C0CYCTRKRD - Channel 0 CYCTRK READ B/D/F/Type: Address Offset: Default Value: Access: Size: Channel 0 CYCTRK RD Registers. Bit Access 23:21 RO 20:17 RW 16:12 RW 11:8 RW 7:4 RW 3:0 RW Datasheet 0/0/0/MCHBAR 258-25Ah 000000h ...
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C0CYCTRKREFR - Channel 0 CYCTRK REFR B/D/F/Type: Address Offset: Default Value: Access: Size: Channel 0 CYCTRK Refresh Registers. Bit Access 15:13 RO 12:9 RW 8:0 RW 1.9.14 C0REFRCTRL - Channel 0 DRAM Refresh Control B/D/F/Type: Address Offset: Default Value: ...
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Processor Configuration Registers Bit Access 31: 21:20 RW Datasheet (Sheet Default Description Value 06h Rcomp Wait (RCOMPWAIT) This configuration setting indicates the amount of refresh_tick events ...
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Bit Access 19:18 RW 17:16 RW 15: Processor Configuration Registers (Sheet Default Description Value 00b DRAM Refresh Panic Watermark (REFPANICWM) When the refresh count exceeds this level, a refresh request is launched to ...
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... Rank 1 not populated. This register is locked by Intel ME stolen Memory lock. 0b Rank 0 Population (sd0_cr_rankpop0) 1: Rank 0 populated. 0: Rank 0 not populated. This register is locked by Intel ME stolen Memory lock. 000b CKE Pulse Width Requirement in Low Phase (sd0_cr_cke_pw_lh_safe) This configuration register indicates CKE pulse width requirement in low phase. ...
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Bit Access 13: 1.9.16 C0ODTCTRL - Channel 0 ODT Control B/D/F/Type: Address Offset: Default Value: Access: Size: Bit Access 31:12 RO 11:8 RW 7 (Sheet Default Value 2h ...
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Processor Configuration Registers 1.9.17 C0DTC - Channel 0 DRAM Throttling Control B/D/F/Type: Address Offset: Default Value: Access: Size: Programmable Event weights are input into the averaging filter. Each Event weight is an normalized 8-bit value that the BIOS must program. ...
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C0DTPEW - Channel 0 DRAM Rank Throttling Passive Event B/D/F/Type: Address Offset: Default Value: Access: Size: Programmable Event weights are input into the averaging filter. Each Event weight is an normalized 8-bit value that the BIOS must program. The ...
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... Description Value 0000h Reserved 00h Reserved 00h Reserved 00h Reserved 00h Reserved 00h Reserved 00h Reserved 0/0/0/MCHBAR 600-601h 0000h RW- bits Default Description Value 000000b Reserved 000h Channel 1 DRAM Rank Boundary Address 0 (C1DRBA0) See C0DRB0. This register is locked by Intel ME stolen Memory lock. 99 ...
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... Channel 1 DRAM Rank Boundary Address 1 (C1DRBA1) See C0DRB1. This register is locked by Intel ME stolen Memory lock. 0/0/0/MCHBAR 604-605h 0000h RW- bits Default Value 000000b Reserved 000h Channel 1 DRAM Rank Boundary Address 2 (C1DRBA2) See C0DRB2. This register is locked by Intel ME stolen Memory lock. Processor Configuration Registers Description Description Datasheet ...
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... This register is locked by Intel ME stolen Memory lock. 0/0/0/MCHBAR 608-609h 0000h RW-L 16 bits Default Value 00h Channel 1 DRAM Rank-1 Attributes (C1DRA1) See C0DRA1. This register is locked by Intel ME stolen Memory lock. 00h Channel 1 DRAM Rank-0 Attributes (C1DRA0) See C0DRA0. This register is locked by Intel ME stolen Memory lock. Description Description 101 ...
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... Default Description Value 00h Channel 1 DRAM Rank-3 Attributes (C1DRA3) See C0DRA3. This register is locked by Intel ME stolen Memory lock. 00h Channel 1 DRAM Rank-2 Attributes (C1DRA2) See C0DRA2. This register is locked by Intel ME stolen Memory lock. 0/0/0/MCHBAR 650-651h 0000h RO bits Default Description Value 00000b ...
Page 103
Processor Configuration Registers 1.9.27 C1CYCTRKACT - Channel 1 CYCTRK ACT B/D/F/Type: Address Offset: Default Value: Access: Size: Channel 1 CYCTRK ACT. Bit Access 31:28 RO 27: 20:17 RW 16:13 RW 12:9 RW 8:0 RW Datasheet 0/0/0/MCHBAR 652-655h ...
Page 104
C1CYCTRKWR - Channel 1 CYCTRK WR B/D/F/Type: Address Offset: Default Value: Access: Size: Channel 1 CYCTRK WR Bit Access 15:12 RW 11:8 RW 7:4 RW 3:0 RW 104 Processor Configuration Registers 0/0/0/MCHBAR 656-657h 0000h RW 16 bits Default Description ...
Page 105
Processor Configuration Registers 1.9.29 C1CYCTRKRD - Channel 1 CYCTRK READ B/D/F/Type: Address Offset: Default Value: Access: Size: Channel 1 CYCTRK READ Bit Access 23:21 RO 20:17 RW 16:12 RW 11:8 RW 7:4 RW 3:0 RW Datasheet 0/0/0/MCHBAR 658-65Ah 000000h RO; ...
Page 106
... Rank 1 populated This register is locked by Intel ME stolen Memory lock. 0b Rank 0 Population (sd1_cr_rankpop0) Rank 0 not populated Rank 0 populated This register is locked by Intel ME stolen Memory lock. 000b CKE pulse width requirement in low phase (sd1_cr_cke_pw_lh_safe) This configuration register indicates CKE pulse width requirement in low phase. ...
Page 107
Processor Configuration Registers Bit Access 13: 1.9.31 C1REFRCTRL - Channel 1 DRAM Refresh Control B/D/F/Type: Address Offset: Default Value: Access: Size: Settings to configure the DRAM refresh controller. Bit Access 47 RO 46:44 RW 43:38 ...
Page 108
Bit Access 21:20 RW 19:18 RW 108 Processor Configuration Registers (Sheet Default Description Value 0b Refresh Counter Enable (REFCNTEN) This bit is used to enable the refresh counter to ...
Page 109
Processor Configuration Registers Bit Access 17:16 RW 15:14 RW 13:0 RW Datasheet (Sheet Default Value 00b DRAM Refresh High Watermark (REFHIGHWM) When the refresh count exceeds this level, a refresh request is launched to the scheduler and ...
Page 110
C1ODTCTRL - Channel 1 ODT Control B/D/F/Type: Address Offset: Default Value: Access: Size: ODT controls. Bit Access 31:12 RO 11:8 RW 7:4 RW 3:0 RW 110 Processor Configuration Registers 0/0/0/MCHBAR 69C-69Fh 00000000h RO bits Default Description Value ...
Page 111
Processor Configuration Registers 1.9.33 C1DTC - Channel 1 DRAM Throttling Control B/D/F/Type: Address Offset: Default Value: Access: Size: Programmable Event weights are input into the averaging filter. Each Event weight is an normalized 8-bit value that the BIOS must program. ...
Page 112
C1DTPEW - Channel 1 DRAM Rank Throttling Passive Event B/D/F/Type: Address Offset: Default Value: Access: Size: Programmable Event weights are input into the averaging filter. Each Event weight is an normalized 8-bit value that the BIOS must program. The ...
Page 113
Processor Configuration Registers 1.9.35 C1DTAEW - Channel 1 DRAM Rank Throttling Active Event B/D/F/Type: Address Offset: Default Value: Access: Size: Programmable Event weights are input into the averaging filter. Each Event weight is an normalized 8-bit value that the BIOS ...
Page 114
DDRMPLL1 - DDR PLL BIOS B/D/F/Type: Address Offset: Default Value: Access: Size: DDR PLL BIOS Registers Settings Encoding[7:0] Data edge rate in MHz 0Ch: 800 MHz 10h: 1066 MHz Bit Access 15: 9:8 RW ...
Page 115
Processor Configuration Registers Register Name Register Symbol Thermal SMI Command TSMICMD Thermal SCI Command TSCICMD Thermal INTR Command TINTRCMD External Thermal Sensor EXTTSCS Control and Status MCH Thermal Sensor Watch MCHTSWDT Dog Timer Memory TDP Controller MEMTDPCTW Registers Memory TDP ...
Page 116
TSC1 - Thermal Sensor Control 1 B/D/F/Type: Address Offset: Default Value: Access: Size: BIOS Optimal Default This register controls the operation of the internal thermal sensor located in the graphics region of the die. Bit Access 15:14 RO 13:10 ...
Page 117
Processor Configuration Registers Bit Access 0 RW-L 1.10.2 TSS1 - Thermal Sensor Status 1 B/D/F/Type: Address Offset: Default Value: Access: Size: This read only register provides trip point and other status of the thermal sensor. Bit Access 15: ...
Page 118
Bit Access 1.10.3 TR1 - Thermometer Read 1 B/D/F/Type: Address Offset: Default Value: Access: Size: This register generally provides the un-calibrated counter value from the thermometer circuit when the Thermometer mode is enabled. See ...
Page 119
Processor Configuration Registers 1.10.4 TOF1 - Thermometer Offset 1 B/D/F/Type: Address Offset: Default Value: Access: Size: This register is used for programming the thermometer offset. Bit Access 7:0 RW 1.10.5 RTR1 - Relative Thermometer Read 1 B/D/F/Type: Address Offset: Default ...
Page 120
TSTTPA1 - Thermal Sensor Temperature Trip Point A1 B/D/F/Type: Address Offset: Default Value: Access: Size: This register: 1. Sets the target values for some of the trip points in thermometer mode. See also TST [Direct DAC Connect Test Enable]. ...
Page 121
Processor Configuration Registers 1.10.7 TSTTPB1 - Thermal Sensor Temperature Trip Point B1 B/D/F/Type: Address Offset: Default Value: Access: Size: This register sets the target values for some of the trip points in the Thermometer mode. See also TSTTPA1. Bit Access ...
Page 122
HWTHROTCTRL1 - Hardware Throttle Control 1 B/D/F/Type: Address Offset: Default Value: Access: Size: Bit Access 7 RW RW-L 4 RW-L 3 RW-L 2 RW-O 122 Processor Configuration Registers 0/0/0/MCHBAR 101Ch 00h RW-L; RO; RW-O ...
Page 123
Processor Configuration Registers 1.10.9 TIS1 - Thermal Interrupt Status 1 B/D/F/Type: Address Offset: Default Value: Access: Size: This register is used to report which specific error condition resulted in the D2F0 or D2F1 ERRSTS [Thermal Sensor event for SMI/SCI/SERR] or ...
Page 124
Bit Access 8 RWC 7 RWC 4 RWC 3 RWC 2 RWC 1 RWC 124 Processor Configuration Registers (Sheet Default Description Value 0b Was Aux 0 Thermal Sensor Interrupt Event (WA0TSIE trip ...
Page 125
Processor Configuration Registers Bit Access 0 RWC 1.10.10 TERATE - Thermometer Mode Enable and Rate B/D/F/Type: Address Offset: Default Value: Access: Size: This common register helps select between the analog and the thermometer mode and also helps select the DAC ...
Page 126
Bit Access 3:0 RW 126 Processor Configuration Registers Default Description Value 0h Thermometer Mode Enable and Rate (TE) If analog thermal sensor mode is not enabled by setting these bits to 0000b, these bits enable the thermometer mode functions and ...
Page 127
Processor Configuration Registers 1.10.11 TERRCMD - Thermal Error Command B/D/F/Type: Address Offset: Default Value: Access: Size: This register select which errors are generate a SERR DMI interface special cycle, as enabled by ERRCMD [SERR Thermal Sensor event]. The SERR and ...
Page 128
TSMICMD - Thermal SMI Command B/D/F/Type: Address Offset: Default Value: Access: Size: This register selects specific errors to generate a SMI DMI cycle, as enabled by the SMI Error Command Register [SMI on Thermal Sensor Trip]. Bit Access 7:6 ...
Page 129
Processor Configuration Registers 1.10.13 TSCICMD - Thermal SCI Command B/D/F/Type: Address Offset: Default Value: Access: Size: This register selects specific errors to generate a SCI DMI cycle, as enabled by the SCI Error Command Register [SCI on Thermal Sensor Trip]. ...
Page 130
TINTRCMD - Thermal INTR Command B/D/F/Type: Address Offset: Default Value: Access: Size: This register selects specific errors to generate an INT DMI cycle Bit Access 7 ...
Page 131
Processor Configuration Registers 1.10.15 EXTTSCS - External Thermal Sensor Control and Status B/D/F/Type: Address Offset: Default Value: Access: Size: Bit Access 15 RW RW-L 12 RW-L 11 RW-L Datasheet 0/0/0/MCHBAR 10EC-10EDh 0000h RO; RW-O; RW-L 16 bits ...
Page 132
Bit Access 10:8 RW-L 7 RW-L 6 RW-L 5 RW RW-L 132 Processor Configuration Registers (Sheet Default Description Value 000b EXTTSS Programmable MX state (EXTTSMXST) MX state to ...
Page 133
Processor Configuration Registers 1.10.16 MCHTSWDT - Memory Controller Thermal Sensor Watch Dog Timer B/D/F/Type: Address Offset: Default Value: Access: Size: When thermally hot tripped and memory controller throttling is enabled, this register allows the value in the TSWDT0[Delta] field to ...
Page 134
MTDPCCRWTWHOTTH - Memory TDP Controller Combined RD/WR Thermal Weight Hot Thresholds B/D/F/Type: Address Offset: Default Value: Access: Size: The settings in these registers apply to the combined memory Rd/Wr thermal weight trackers in both ch0 and ch1. The range ...
Page 135
Processor Configuration Registers Bit Access 15:0 RW Datasheet (Sheet Default Description Value 0000h Memory Combined Rd/Wr Thermal Weight Hot-1 Threshold (MemCRWTWHotM1Th) The Hot-1 thermal weight threshold used for memory combined Rd/Wr thermal weight tracking. This 16-bit value ...
Page 136
MTDPCCRWTWHOTTH2 - Memory TDP Controller Combined RD/WR Thermal Weight Hot Thresholds 2 B/D/F/Type: Address Offset: Default Value: Access: Size: Bit Access 31:16 RW 15:0 RW 136 Processor Configuration Registers 0/0/0/MCHBAR 2F4-2F7h 00000000h RW 32 bits Default Description Value 0000h ...
Page 137
Processor Configuration Registers 1.10.20 MTDPCCRWTWHOTTH3 - Memory TDP Controller Combined RD/WR Thermal Weight Hot Thresholds 3 B/D/F/Type: Address Offset: Default Value: Access: Size: Bit Access 31:16 RW 15:0 RW Datasheet 0/0/0/MCHBAR 2F8-2FBh 00000000h RW 32 bits Default Description Value 0000h ...
Page 138
MTDPCCRWTWHOTTH4 - Memory TDP Controller Combined RD/WR Thermal Weight Hot Thresholds 4 B/D/F/Type: Address Offset: Default Value: Access: Size: Bit Access 31:16 RW 15:0 RW 138 Processor Configuration Registers 0/0/0/MCHBAR 2FC-2FFh 00000000h RW; 32 bits Default Description Value Memory ...
Page 139
Processor Configuration Registers 1.10.22 MTDPCHOTTHINT - Memory TDP Controller Hot Throttled Intervals B/D/F/Type: Address Offset: Default Value: Access: Size: These registers control the duty cycle of throttling. The total throttled + non-throttled interval can be from 256 ...
Page 140
MTDPCHOTTHINT2 - Memory TDP Controller Hot Throttled Intervals 2 B/D/F/Type: Address Offset: Default Value: Access: Size: Bit Access 31:24 RW 23:16 RW 15:8 RW 7:0 RW 140 Processor Configuration Registers 0/0/0/MCHBAR 304-307h 00000000h RW 32 bits Default Description Value ...
Page 141
Processor Configuration Registers 1.10.24 MTDPCTLAUXTNTINT - Memory TDP Controller Aux and Throttle-NonThrottle Intervals B/D/F/Type: Address Offset: Default Value: Access: Size: Bit Access 31:24 RO 23:20 RW 19:16 RW 15:10 RO 9:8 RW 7:0 RW 1.10.25 MTDPCMISC - Memory TDP Controller ...
Page 142
Bit Access 7:4 RO 3:0 RW 1.10.26 TSFUSE - Thermal Sensor Fuses B/D/F/Type: Address Offset: Default Value: Access: Size: This register reads the thermal sensor fuses. Calibration is a linear ...
Page 143
Processor Configuration Registers 1.11 MCHBAR Render Thermal Throttling Controls Register Name Thermal State Control Render Standby State Control VID Control Watchdog Timer For Thermal Sensor Trip Watchdog Timer Based Px Step Size 1.11.1 THERMSTCTL – Render Thermal State Control B/D/F/Type: ...
Page 144
RSTDBYCTL - Render Standby State Control B/D/F/Type: Address Offset: Default Value: Access: Size: RS2 = Render Standby with Context Restore. Bit Access ...
Page 145
Processor Configuration Registers 1.11.3 VIDCTL - VID Control B/D/F/Type: Address Offset: Default Value: Access: Size: This register bit field shall contain the default value unless otherwise indicated in the BIOS specification. Bit Access 31:24 RW 23:16 RW 15:8 RW 7:0 ...
Page 146
Device 0 MCHBAR ACPI Power Management Controls Register Name C3/C6 EntryTimers Self-Refresh Channel Status PM Memory Subsystem Power Management Configuration 1.12.1 C3C6ET - C3/C6 EntryTimers B/D/F/Type: Address Offset: Default Value: Access: Size: Bit Access 31:30 RO 29:22 RW 21:16 ...
Page 147
Processor Configuration Registers 1.12.2 SLFRCS - Self-Refresh Channel Status B/D/F/Type: Address Offset: Default Value: Access: Size: This register is Reset by PWROK only. Bit Access 15 RWC-P 0 RWC-P 1.12.3 DSLFRC - PM Memory Subsystem B/D/F/Type: Address Offset: ...
Page 148
PMCFG - Power Management Configuration B/D/F/Type: Address Offset: Default Value: Access: Size: This Register bit field shall contain the default unless otherwise indicated in the BIOS Specification. 1.13 PCI Device1 Device 1 contains the controls associated with the PCI ...
Page 149
Processor Configuration Registers Register Register Name Symbol Revision RID1 Identification Class Code CC1 Cache Line Size CL1 Header Type HDR1 Primary Bus PBUSN1 Number Secondary Bus SBUSN1 Number Subordinate Bus SUBUSN1 Number I/O Base Address IOBASE1 I/O Limit Address IOLIMIT1 ...
Page 150
Register Register Name Symbol Subsystem ID and SS_CAPID Vendor ID Capabilities Subsystem ID and SS Subsystem Vendor ID Message Signaled MSI_CAPID Interrupts Capability ID Message Control MC Message Address MA Message Data MD PCI Express-G PEG_CAPL Capability List PCI Express-G ...
Page 151
... RO Datasheet 0/1/0/PCI 0-1h 8086h RO 16 bits Default Description Value 8086h Vendor Identification (VID1) PCI standard identification for Intel. 0/1/0/PCI 2-3h 0045h RO 16 bits Default Description Value 004h Device Identification Number (DID1(UB)) Identifier assigned to the processor Device 1 (virtual PCI-to-PCI bridge, PCI Express Graphics port). ...
Page 152
PCICMD1 - PCI Command B/D/F/Type: Address Offset: Default Value: Access: Size: Bit Access 15: 152 Processor Configuration Registers 0/1/0/PCI 4-5h 0000h RO bits (Sheet Default ...
Page 153
Processor Configuration Registers Bit Access Datasheet (Sheet Default Description Value 0b Parity Error Response Enable (PERRE) Controls whether or not the Master Data ...
Page 154
PCISTS1 - PCI Status B/D/F/Type: Address Offset: Default Value: Access: Size: This register reports the occurrence of error conditions associated with primary side of the “virtual” Host-PCI Express bridge embedded within the processor. Bit Access RWC ...
Page 155
Processor Configuration Registers Bit Access 2:0 RO Datasheet (Sheet Default Description Value 0b Fast Back-to-Back (FB2B) Not Applicable or Implemented. Hard wired Reserved 0b ...
Page 156
... Stepping Revision ID (SRID) This register contains the revision number of the CPU. The SRID is a 8-bit hardwired value assigned by Intel, based on product’s stepping. The SRID is not a directly addressable PCI register. The SRID value is reflected through the RID register when appropriately addressed. ...
Page 157
Processor Configuration Registers 1.13.6 CC1 - Class Code B/D/F/Type: Address Offset: Default Value: Access: Size: This register identifies the basic function of the device, a more specific sub-class, and a register- specific programming interface. Bit Access 23:16 RO 15:8 RO ...
Page 158
HDR1 - Header Type B/D/F/Type: Address Offset: Default Value: Access: Size: This register identifies the header layout of the configuration space. No physical register exists at this location. Bit Access 7:0 RO 1.13.9 PBUSN1 - Primary Bus Number B/D/F/Type: ...
Page 159
Processor Configuration Registers 1.13.10 SBUSN1 - Secondary Bus Number B/D/F/Type: Address Offset: Default Value: Access: Size: This register identifies the bus number assigned to the second bus side of the “virtual” bridge, i.e., to PCI Express-G. This number is programmed ...
Page 160
IOBASE1 - I/O Base Address B/D/F/Type: Address Offset: Default Value: Access: Size: This register controls the CPU to PCI Express-G I/O access routing based on the following formula: IO_BASE=< address =<IO_LIMIT Only upper 4 bits are programmable. For the ...
Page 161
Processor Configuration Registers 1.13.14 SSTS1 - Secondary Status B/D/F/Type: Address Offset: Default Value: Access: Size: SSTS1 is a 16-bit status register that reports the occurrence of error conditions associated with secondary side (i.e., PCI Express-G side) of the “virtual” PCI-to-PCI ...
Page 162
Bit Access 5 RO 4:0 RO 1.13.15 MBASE1 - Memory Base Address B/D/F/Type: Address Offset: Default Value: Access: Size: This register controls the CPU to PCI Express-G non-prefetchable memory access routing based on the following formula: MEMORY_BASE=< address =<MEMORY_LIMIT The ...
Page 163
Processor Configuration Registers software. For the purpose of address decode address bits A[19:0] are assumed to be FFFFFh. Thus, the top of the defined memory address range is at the top of a 1-MB aligned memory block. Note: Memory range ...
Page 164
Bit Access 15:4 RW 3:0 RO 1.13.18 PMLIMIT1 - Prefetchable Memory Limit Address B/D/F/Type: Address Offset: Default Value: Access: Size: This register in conjunction with the corresponding Upper Limit Address register controls the CPU to PCI Express-G prefetchable memory access ...
Page 165
Processor Configuration Registers 1.13.19 PMBASEU1 - Prefetchable Memory Base Address Upper B/D/F/Type: Address Offset: Default Value: Access: Size: The functionality associated with this register is present in the PEG design implementation. This register in conjunction with the corresponding Upper Base ...
Page 166
The upper 12 bits of this register are read/write and correspond to address bits A[31:20] of the 40- bit address. The lower 8 bits of the Upper Limit Address register are read/write and correspond to address bits A[39:32] of the ...
Page 167
Processor Configuration Registers 1.13.22 INTRLINE1 - Interrupt Line B/D/F/Type: Address Offset: Default Value: Access: Size: This register contains interrupt line routing information. The device itself does not use this value, rather it is used by device drivers and operating systems ...
Page 168
BCTRL1 - Bridge Control B/D/F/Type: Address Offset: Default Value: Access: Size: This register provides extensions to the PCICMD1 register that are specific to PCI-PCI bridges. The BCTRL provides additional control for the secondary interface (i.e., PCI Express-G) as well ...
Page 169
Processor Configuration Registers Bit Access Datasheet (Sheet Default Description Value 0b VGA Enable (VGAEN) Controls the routing of CPU initiated transactions targeting VGA compatible I/O and memory address ranges. ...
Page 170
PM_CAPID1 - Power Management Capabilities B/D/F/Type: Address Offset: Default Value: Access: Size: Bit Access 31: 24: 18:16 RO 15:8 RO 7:0 RO 170 Processor Configuration Registers 0/1/0/PCI ...
Page 171
Processor Configuration Registers 1.13.26 PM_CS1 - Power Management Control/Status B/D/F/Type: Address Offset: Default Value: Access: Size: Bit Access 31: 14: RW-S 7 Datasheet 0/1/0/PCI 84-87h 00000008h RO; RW-S; ...
Page 172
Bit Access 1:0 RW 172 Processor Configuration Registers (Sheet Default Description Value 00b Power State (PS) Indicates the current power state of this device and can be used to set the device into a new power state. ...
Page 173
Processor Configuration Registers 1.13.27 SS_CAPID - Subsystem ID and Vendor ID Capabilities B/D/F/Type: Address Offset: Default Value: Access: Size: This capability is used to uniquely identify the subsystem where the PCI device resides. Because this device is an integrated part ...
Page 174
MSI_CAPID - Message Signaled Interrupts Capability ID B/D/F/Type: Address Offset: Default Value: Access: Size: When a device supports MSI it can generate an interrupt request to the processor by writing a predefined data item (a message predefined ...
Page 175
Processor Configuration Registers Bit Access 6 1.13. Message Address B/D/F/Type: Address Offset: Default Value: Access: Size: Bit Access 31:2 RW 1:0 RO Datasheet (Sheet Default Value 000b Multiple Message Enable ...
Page 176
MD - Message Data B/D/F/Type: Address Offset: Default Value: Access: Size: Bit Access 15:0 RW 1.13.33 PEG_CAPL - PCI Express-G Capability List B/D/F/Type: Address Offset: Default Value: Access: Size: Enumerates the PCI Express capability structure. Bit Access 15:8 RO ...
Page 177
Processor Configuration Registers 1.13.34 PEG_CAP - PCI Express-G Capabilities B/D/F/Type: Address Offset: Default Value: Access: Size: Indicates PCI Express device capabilities. Bit Access 13 RW-O 7:4 RO 3:0 RO Datasheet 0/1/0/PCI A2-A3h 0142h RO; ...
Page 178
DCAP - Device Capabilities B/D/F/Type: Address Offset: Default Value: Access: Size: Indicates PCI Express device capabilities. Bit Access 31: 14 4:3 RO 2:0 RO 178 Processor Configuration Registers 0/1/0/PCI A4-A7h 00008000h RO 32 ...
Page 179
Processor Configuration Registers 1.13.36 DCTL - Device Control B/D/F/Type: Address Offset: Default Value: Access: Size: Provides control for PCI Express device specific capabilities. The error reporting enable bits are in reference to errors detected by this device, not error messages ...
Page 180
Bit Access 1.13.37 DSTS - Device Status B/D/F/Type: Address Offset: Default Value: Access: Size: Reflects status corresponding to controls in the Device Control register. The error reporting bits are in reference to errors detected by this ...
Page 181
Processor Configuration Registers Bit Access 2 RWC 1 RWC 0 RWC 1.13.38 LCAP - Link Capabilities B/D/F/Type: Address Offset: Default Value: Access: Size: Indicates PCI Express device specific capabilities. Bit Access 31:24 RO 23:22 RO Datasheet (Sheet ...
Page 182
Bit Access 182 Processor Configuration Registers (Sheet Default Description Value 1b Link Bandwidth Notification Capability (LBNC) A value of 1b indicates support for the Link Bandwidth Notification status and ...
Page 183
Processor Configuration Registers Bit Access 17:15 RW-O 14:12 RO 11:10 RW-O 9:4 RW-O Datasheet (Sheet Default Value 010b L1 Exit Latency (L1ELAT) Indicates the length of time this Port requires to complete the transition from L1 to ...
Page 184
Bit Access 3:0 RW-O 184 Processor Configuration Registers (Sheet Default Description Value 1h Max Link Speed (MLS) Supported Link Speed – This field indicates the supported Link speed(s) of the associated Port. Defined encodings are: 0001b2.5-GT/s Link ...
Page 185
Processor Configuration Registers 1.13.39 LCTL - Link Control B/D/F/Type: Address Offset: Default Value: Access: Size: Allows control of PCI Express link. Bit Access 15: Datasheet 0/1/0/PCI B0-B1h 0000h RO; RW; RW-SC ...
Page 186
Bit Access RW- 186 Processor Configuration Registers (Sheet Default Description Value 0b Extended Synch (ES Standard Fast Training Sequence (FTS Forces the ...
Page 187
Processor Configuration Registers Bit Access 1:0 RW 1.13.40 LSTS - Link Status B/D/F/Type: Address Offset: Default Value: Access: Size: Indicates PCI Express link status. Bit Access 15 RWC Datasheet (Sheet Default Description Value 00b Active State PM ...
Page 188
Bit Access 14 RWC 9:4 RO 188 Processor Configuration Registers Default Description Value 0b Link Bandwidth Management Status (LBWMS) This bit is set hardware to indicate that either of ...
Page 189
Processor Configuration Registers Bit Access 3:0 RO 1.13.41 SLOTCAP - Slot Capabilities B/D/F/Type: Address Offset: Default Value: Access: Size: PCI Express Slot related registers allow for the support of Hot Plug. Bit Access 31:19 RW 16:15 ...
Page 190
Bit Access 14:7 RW 190 Processor Configuration Registers (Sheet Default Description Value 00h Slot Power Limit Value (SPLV) In combination with the Slot ...
Page 191
Processor Configuration Registers 1.13.42 SLOTCTL - Slot Control B/D/F/Type: Address Offset: Default Value: Access: Size: PCI Express Slot related registers allow for the support of Hot Plug. Bit Access 15: Datasheet 0/1/0/PCI B8-B9h ...
Page 192
Bit Access 9 192 Processor Configuration Registers (Sheet Default Description Value 00b Reserved Power Indicator Control (PIC Power Indicator is implemented, writes to this field set the Power ...
Page 193
Processor Configuration Registers Bit Access 1.13.43 SLOTSTS - Slot Status B/D/F/Type: Address Offset: Default Value: Access: Size: PCI Express Slot related registers allow for the support of Hot Plug. Bit Access 15:9 ...
Page 194
Bit Access 194 Processor Configuration Registers (Sheet Default Description Value 0b Reserved for Electromechanical Interlock Status (EIS Electromechanical Interlock is implemented, this bit indicates the current status ...
Page 195
Processor Configuration Registers Bit Access 3 RWC Datasheet (Sheet Default Value 0b Presence Detect Changed (PDC) A pulse indication that the inband presence detect state has changed. This bit is set ...
Page 196
RCTL - Root Control B/D/F/Type: Address Offset: Default Value: Access: Size: Allows control of PCI Express Root Complex specific parameters. The system error control bits in this register determine if corresponding SERRs are generated when our device detects an ...
Page 197
Processor Configuration Registers 1.13.45 RSTS - Root Status B/D/F/Type: Address Offset: Default Value: Access: Size: Provides information about PCI Express Root Complex specific parameters. Bit Access 31: RWC 15:0 RO Datasheet 0/1/0/PCI C0-C3h 00000000h RO; RWC ...
Page 198
LCTL2 - Link Control 2 B/D/F/Type: Address Offset: Default Value: Access: Size: Bit Access 15: RW-S 11 RW-S 10 RW-S 198 Processor Configuration Registers 0/1/0/PCI D0-D1h 0002h RO; RW- bits (Sheet Default ...
Page 199
Processor Configuration Registers Bit Access 9:7 RW RW-S Datasheet (Sheet Default Description Value 000b Transmit Margin (txmargin) This field controls the value of the non-de-emphasized voltage level at the Transmitter pins. This ...
Page 200
Bit Access 3:0 RW 1.13.47 LSTS2 - Link Status 2 B/D/F/Type: Address Offset: Default Value: Access: Size: Bit Access 15 200 Processor Configuration Registers (Sheet Default Description Value 2h Target Link Speed (TLS) For ...