CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 348

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

348
21:16
15:13
12:8
Bit
22
Access
RO
RO
RO
RO
Default
Value
000b
23h
02h
0b
Zero Length Read (ZLR)
0 = Indicates the remapping hardware unit blocks (and treats
1 = Indicates the remapping hardware unit supports zero
Maximum Guest Address Width (MGAW)
This field indicates the maximum DMA virtual addressability
supported by remapping hardware.
The Maximum Guest Address Width (MGAW) is computed as
(N+1), where N is the value reported in this field. For
example, a hardware implementation supporting 48-bit
MGAW reports a value of 47 (101111b) in this field.
If the value in this field is X, not translated and translated
DMA requests to addresses above 2^^(x+1) - 1 are always
blocked by hardware. Translation requests to address above
2^^(X+1) - 1 from allowed devices return a null Translation
Completion Data Entry with R=W=0.
Guest addressability for a given DMA request is limited to the
minimum of the value reported through this field and the
adjusted guest address width of the corresponding page-table
structure. (Adjusted guest address widths supported by
hardware are reported through the SAGAW field).
Reserved
Supported Adjusted Guest Address Width (SAGAW)
This 5-bit field indicates the supported adjusted guest address
widths (which in turn represents the levels of page-table
walks for the 4-KB base page size) supported by the hardware
implementation.
A value of 1 in any of these bits indicates the corresponding
adjusted guest address width is supported. The adjusted
guest address widths corresponding to various bit positions
within this field are:
0: 30-bit AGAW (2-level page-table)
1: 39-bit AGAW (3-level page-table)
3: 57-bit AGAW (5-level page-table)
4: 64-bit AGAW (6-level page-table)
Software must ensure that the adjusted guest address width
used to set up the page tables is one of the supported guest
address widths reported in this field.
as fault) zero length DMA read requests to write-only
pages.
length DMA read requests to write-only pages.
(Sheet 3 of 5)
Description
Processor Configuration Registers
Datasheet