CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 165

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

Processor Configuration Registers
1.13.19
1.13.20
Datasheet
PMBASEU1 - Prefetchable Memory Base Address Upper
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
The functionality associated with this register is present in the PEG design
implementation.
This register in conjunction with the corresponding Upper Base Address register
controls the CPU to PCI Express-G prefetchable memory access routing based on the
following formula:
The upper 12 bits of this register are read/write and correspond to address bits
A[31:20] of the 40-bit address. The lower 8 bits of the Upper Base Address register are
read/write and correspond to address bits A[39:32] of the 40-bit address. This register
must be initialized by the configuration software. For the purpose of address decode
address bits A[19:0] are assumed to be 0. Thus, the bottom of the defined memory
address range is aligned to a 1-MB boundary.
PMLIMITU1 - Prefetchable Memory Limit Address Upper
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
The functionality associated with this register is present in the PEG design
implementation.
This register in conjunction with the corresponding Upper Limit Address register
controls the CPU to PCI Express-G prefetchable memory access routing based on the
following formula:
PREFETCHABLE_MEMORY_BASE =< address =< PREFETCHABLE_MEMORY_LIMIT
PREFETCHABLE_MEMORY_BASE =< address =< PREFETCHABLE_MEMORY_LIMIT
31:0
Bit
Access
RW
00000000h Prefetchable Memory Base Address (MBASEU)
Default
Value
Corresponds to A[63:32] of the lower limit of the
prefetchable memory range that is passed to PCI Express-
G.
0/1/0/PCI
28-2Bh
00000000h
RW
32 bits
0/1/0/PCI
2C-2Fh
00000000h
RW
32 bits
Description
165