CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 279

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

Processor Configuration Registers
1.18.15
Datasheet
PLMBASE_REG - Protected Low-Memory Base Register
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
Register to setup the base address of DMA protected low-memory region. This register
must be setup before enabling protected memory through PMEN_REG, and must not be
updated when protected memory regions are enabled.
When LT.CMD.LOCK.PMRC command is invoked, this register is locked (treated RO).
When LT.CMD.UNLOCK.PMRC command is invoked, this register is unlocked (treated
RW).
This register is always treated as RO for implementations not supporting protected low
memory region (PLMR field reported as 0 in the Capability register). The alignment of
the protected low memory region base depends on the number of reserved bits (N) of
this register.
Software may determine the value of N by writing all 1's to this register, and finding
most significant zero bit position with 0 in the value read back from the register. Bits
N:0 of this register is decoded by hardware as all 0’s.
31:21
20:0
Bit
0
Access
RO
RW
RO
000000h
Default
Value
000h
0h
Protected Region Status (PRS)
This field indicates the status of protected memory region.
0 = Protected memory region(s) not enabled.
1 = Protected memory region(s) enabled.
Protected Low-Memory Base (PLMB)
This register specifies the base of size aligned, protected low-
memory region in system memory. The protected low-
memory region has a minimum size of 2 MB and must be size
aligned.
Reserved
0/0/0/VC0PREMAP
68-6Bh
00000000h
RO; RW
32 bits
(Sheet 2 of 2)
Description
279