CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 176

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

1.13.32
1.13.33
176
MD - Message Data
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
PEG_CAPL - PCI Express-G Capability List
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
Enumerates the PCI Express capability structure.
15:0
15:8
Bit
7:0
Bit
Access
Access
RW
RO
RO
Default
Default
Value
Value
0000h
00h
10h
Pointer to Next Capability (PNC)
This value terminates the capabilities list. The Virtual Channel
capability and any other PCI Express specific capabilities that
are reported via this mechanism are in a separate capabilities
list located entirely within PCI Express Extended Configuration
Space.
Capability ID (CID)
Identifies this linked list item (capability structure) as being
for PCI Express registers.
Message Data (MD)
Base message data pattern assigned by system software
and used to handle an MSI from the device.
When the device must generate an interrupt request, it
writes a 32-bit value to the memory address specified in the
MA register. The upper 16 bits are always set to 0. The lower
16 bits are supplied by this register.
0/1/0/PCI
98-99h
0000h
RW
16 bits
0/1/0/PCI
A0-A1h
0010h
RO
16 bits
Processor Configuration Registers
Description
Description
Datasheet