CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 226

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

1.16.4
226
Bit
5
4
3
2
1
0
Access
RW
RW
RW
RO
RO
RO
PCISTS2 - PCI Status
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
PCISTS is a 16-bit status register that reports the occurrence of a PCI compliant master
abort and PCI compliant target abort.
PCISTS also indicates the DEVSEL# timing that has been set by the IGD.
Bit
15
14
13
Default
Value
0b
0b
0b
0b
0b
0b
Access
RO
RO
RO
FLR, Core
FLR, Core
FLR, Core
RST/
PWR
Core
Core
Core
Default
Value
0b
0b
0b
Video Palette Snooping (VPS)
This bit is hard wired to 0 to disable snooping.
Memory Write and Invalidate Enable (MWIE)
invalidate commands.
Special Cycle Enable (SCE)
This bit is hard wired to 0. The IGD ignores Special cycles.
Bus Master Enable (BME)
0 = Disable IGD bus mastering.
1 = Enable the IGD to function as a PCI compliant master.
Memory Access Enable (MAE)
This bit controls the IGD's response to memory space accesses.
0 = Disable.
1 = Enable.
I/O Access Enable (IOAE)
This bit controls the IGD's response to I/O space accesses.
0 = Disable.
1 = Enable.
hard wired to 0. The IGD does not support memory write and
(Sheet 2 of 2)
Detected Parity Error (DPE)
Since the IGD does not detect parity, this bit is always hard
wired to 0.
Signaled System Error (SSE)
The IGD never asserts SERR#, therefore this bit is hard
wired to 0.
Received Master Abort Status (RMAS)
The IGD never gets a Master Abort, therefore this bit is hard
wired to 0.
0/2/0/PCI
6-7h
0090h
RO
16 bits
(Sheet 1 of 2)
Description
Processor Configuration Registers
Description
Datasheet