CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 201

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

Processor Configuration Registers
1.13.48
Datasheet
PEGLC - PCI Express-G Legacy Control
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
Controls functionality that is needed by Legacy (non-PCI Express aware) OS's during
run time.
31:3
Bit
2
1
0
Access
RW
RW
RW
RO
00000000h
Default
Value
0b
0b
0b
Reserved
PME GPE Enable (PMEGPE)
0 = Do not generate GPE PME message when PME is
1 = Generate a GPE PME message when PME is received.
Hot-Plug GPE Enable (HPGPE)
0 = Do not generate GPE Hot-Plug message when Hot-
1 = Generate a GPE Hot-Plug message when Hot-Plug
General Message GPE Enable (GENGPE)
0 = Do not forward received GPE assert/deassert
1 = Forward received GPE assert/deassert messages.
0/1/0/PCI
EC-EFh
00000000h
RO; RW
32 bits
received.
This enables the processor to support PMEs on the
PEG port under legacy OSs.
Plug event is received.
Event is received. This enables the processor to
support Hot-Plug on the PEG port under legacy OSs
messages.
Description
201