CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 290

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

1.18.29
290
IOTLB_REG - IOTLB Invalidate Register
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
Register to control page-table entry caching. The act of writing the upper byte of the
IOTLB_REG with IVT field set causes the hardware to perform the IOTLB
invalidation.There is an IOTLB_REG for each IOTLB Invalidation unit supported by
hardware.
Bit
63
Access
RW
Default
Value
0h
Invalidate IOTLB (IVT)
Software requests IOTLB invalidation by setting this field.
Software must also set the requested invalidation
granularity by programming the IIRG field.
Hardware clears the IVT field to indicate the invalidation
request is complete. Hardware also indicates the
granularity at which the invalidation operation was
performed through the IAIG field.
Software must not submit another invalidation request
through this register while the IVT field is set, nor update
the associated Invalidate Address register. Software must
not submit IOTLB invalidation requests through any of the
IOTLB invalidation units when there is a context-cache
invalidation request pending at this DMA-remapping
hardware unit.
When more than one IOTLB invalidation units are
supported by a DMA-remapping hardware unit, software
may submit IOTLB invalidation request through any of the
currently free units while there are pending requests on
other units.
Hardware implementations reporting write-buffer flushing
requirement (RWBF=1 in Capability register) must
implicitly perform a write buffer flushing before reporting
invalidation complete to software through the IVT field.
0/0/0/VC0PREMAP
108-10Fh
0000000000000000h
RO; RW
64 bits
(Sheet 1 of 3)
Processor Configuration Registers
Description
Datasheet