CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 117

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

Processor Configuration Registers
1.10.2
Datasheet
TSS1 - Thermal Sensor Status 1
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
This read only register provides trip point and other status of the thermal sensor.
15:11
7:6
Bit
Bit
10
9
8
5
4
3
0
Access
Access
RW-L
RO
RO
RO
RO
RO
RO
RO
RO
Default
Default
Value
Value
0b
00h
00b
0b
0b
0b
0b
0b
0b
Thermal Sensor Enable (TSE)
This bit enables the thermal sensor logic in the core. The
thermal sensor circuit EBB is enabled on PWROK. Lockable via
TSTTPA1 Bit 30, TIC1 Bit 7.
0 = Disabled
1 = Enabled
Reserved
Thermometer Mode Output Valid (TMOV)
0 = The Thermometer mode is off, or the temperature is out
1 = The Thermometer mode is able to converge to a
Direct Catastrophic Comparator Read (DCCR)
This bit reads the output of the Catastrophic comparator
directly, without latching via the Thermometer mode circuit.
Used for testing.
Reserved
Reserved
Catastrophic Trip Indicator (CTI)
A 1 indicates that the internal thermal sensor temperature is
above the catastrophic setting.
Hot Trip Indictor (HTI)
A 1 indicates that the internal thermal sensor temperature is
above the Hot setting.
Aux3 Trip Indicator (A3TI)
A 1 indicates that the internal thermal sensor temperature is
above the Aux3 setting.
0/0/0/MCHBAR
1004-1005h
0000h
RO
16 bits
of range, or the TR register is being looked at before a
temperature conversion has had time to complete.
temperature and the TR register is reporting a
reasonable estimate of the thermal sensor temperature.
(Sheet 2 of 2)
(Sheet 1 of 2)
Description
Description
117