CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 382

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

1.20.29
382
IOTLB_REG - IOTLB Invalidate Register
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
Register to invalidate IOTLB. The act of writing the upper byte of the IOTLB_REG with
the IVT field Set causes the hardware to perform the IOTLB invalidation.
62:60
Bit
63
Access
RW
RW
Default
Value
000b
0b
Invalidate IOTLB (IVT)
Software requests IOTLB invalidation by setting this field.
Software must also set the requested invalidation
granularity by programming the IIRG field.
Hardware clears the IVT field to indicate the invalidation
request is complete. Hardware also indicates the
granularity at which the invalidation operation was
performed through the IAIG field.
Software must not submit another invalidation request
through this register while the IVT field is Set, nor update
the associated Invalidate Address register.
Software must not submit IOTLB invalidation requests
when there is a context-cache invalidation request pending
at this remapping hardware unit.
Hardware implementations reporting a write-buffer flushing
requirement (RWBF=1 in Capability register) must
implicitly perform a write buffer flushing before invalidating
the IOTLB.
IOTLB Invalidation Request Granularity (IIRG)
When requesting hardware to invalidate the IOTLB (by
setting the IVT field), software writes the requested
invalidation granularity through this field. The following are
the encodings for the field.
000:Reserved.
001:Global invalidation request.
010:Domain-selective invalidation request. The target
domain-id must be specified in the DID field.
011:Page-selective invalidation request.
The target address, mask and invalidation hint must be
specified in the Invalidate Address register, and the
domain-id must be provided in the DID field.
100 - 111:Reserved.
Hardware implementations may process an invalidation
request by performing invalidation at a coarser granularity
than requested. Hardware indicates completion of the
invalidation request by clearing the IVT field. At that time,
the granularity at which actual invalidation was performed
is reported through the IAIG field.
0/2/0/GFXVTBAR
108-10Fh
0200000000000000h
RO; RW
64 bits
(Sheet 1 of 3)
Processor Configuration Registers
Description
Datasheet