CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 225

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

Processor Configuration Registers
1.16.2
1.16.3
Datasheet
15:11
Bit
10
9
8
7
6
Access
RW
RO
RO
RO
RO
RO
DID2 - Device Identification
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
This register combined with the Vendor Identification register uniquely identifies any
PCI device.
PCICMD2 - PCI Command
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
This 16-bit register provides basic control over the IGD's ability to respond to PCI
cycles. The PCICMD Register in the IGD disables the IGD PCI compliant master
accesses to main memory.
15:0
Bit
Default
Value
00h
0b
0b
0b
0b
0b
Access
RO
FLR, Core
RST/
PWR
Core
Core
Core
Core
Core
Default
Value
0046h
Reserved
Interrupt Disable (INTDIS)
This bit disables the device from asserting INTx#.
0 = Enable the assertion of this device's INTx# signal.
1 = Disable the assertion of this device's INTx# signal. DO_INTx
Fast Back-to-Back (FB2B)
Not Implemented. Hard wired to 0.
SERR Enable (SERRE)
Not Implemented. Hard wired to 0.
Address/Data Stepping Enable (ADSTEP)
Not Implemented. Hard wired to 0.
Parity Error Enable (PERRE)
Not Implemented. Hard wired to 0. Since the IGD belongs to the
category of devices that does not corrupt programs or data in
system memory or hard drives, the IGD ignores any parity error
that it detects and continues with normal operation.
(Sheet 1 of 2)
Device Identification Number (DID)
This is a 16-bit value assigned to the processor Graphics
device.
messages will not be sent to DMI.
0/2/0/PCI
2-3h
0046h
RO
16 bits
0/2/0/PCI
4-5h
0000h
RO; RW
16 bits
Description
Description
225