CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 102

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

1.9.25
1.9.26
102
C1DRA23 - Channel 1 DRAM Rank 2,3 Attributes
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
The operation of this register is detailed in the description for register C0DRA01.
C1CYCTRKPCHG - Channel 1 CYCTRK PCHG
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
Channel 1 CYCTRK Precharge.
15:11
15:8
10:6
5:2
1:0
7:0
Bit
Bit
Access
Access
RW-L
RW-L
RW
RW
RW
RO
Default
Default
00000b
00000b
Value
0000b
Value
00b
00h
00h
Channel 1 DRAM Rank-3 Attributes (C1DRA3)
See C0DRA3.
This register is locked by Intel ME stolen Memory lock.
Channel 1 DRAM Rank-2 Attributes (C1DRA2)
See C0DRA2.
This register is locked by Intel ME stolen Memory lock.
Reserved
Write To PRE Delayed (C1sd_cr_wr_pchg)
This configuration register indicates the minimum allowed
spacing (in DRAM clocks) between the WRITE and PRE
commands to the same rank-bank. Corresponds to tWR at
DDR Spec.
READ To PRE Delayed (C1sd_cr_rd_pchg)
This configuration register indicates the minimum allowed
spacing (in DRAM clocks) between the READ and PRE
commands to the same rank-bank
PRE To PRE Delayed (C1sd_cr_pchg_pchg)
This configuration register indicates the minimum allowed
spacing (in DRAM clocks) between two PRE commands to the
same rank.
0/0/0/MCHBAR
60A-60Bh
0000h
RW-L
16 bits
0/0/0/MCHBAR
650-651h
0000h
RO; RW
16 bits
Description
Description
Processor Configuration Registers
Datasheet