CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 319

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

Processor Configuration Registers
Datasheet
Bit
3
2
1
0
Access
RWC-P
RWC-P
RWC-P
RO-P
Default
Value
0b
0b
0b
0b
Advanced Pending Fault (APF)
When this field is Clear, hardware sets this field when the
first fault record (at index 0) is written to a fault log. At this
time, a fault event is generated based on the programming
of the Fault Event Control register.
Software writing 1 to this field clears it. Hardware
implementations not supporting advanced fault logging
implement this bit as RSVD.
Advanced Fault Overflow (AFO)
Hardware sets this field to indicate advanced fault log
overflow condition. At this time, a fault event is generated
based on the programming of the Fault Event Control
register.
Software writing 1 to this field clears it. Hardware
implementations not supporting advanced fault logging
implement this bit as RSVD.
Primary Pending Fault (PPF)
This field indicates if there are one or more pending faults
logged in the fault recording registers. Hardware computes
this field as the logical OR of Fault (F) fields across all the
fault recording registers of this DMA-remapping hardware
unit.
0 = No pending faults in any of the fault recording registers.
1 = One or more fault recording registers has pending
The FRI field is updated by hardware whenever the PPF field
is set by hardware. Also, depending on the programming of
Fault Event Control register, a fault event is generated when
hardware sets this field.
Primary Fault Overflow (PFO)
Hardware sets this field to indicate overflow of fault
recording registers. Software writing 1 clears this field.
When this field is Set, hardware does not record any new
faults until software clears this field.
faults.
(Sheet 2 of 2)
Description
319