CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 154

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

1.13.4
154
PCISTS1 - PCI Status
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
This register reports the occurrence of error conditions associated with primary side of
the “virtual” Host-PCI Express bridge embedded within the processor.
10:9
Bit
15
14
13
12
11
8
Access
RWC
RO
RO
RO
RO
RO
RO
Default
Value
00b
0b
0b
0b
0b
0b
0b
Detected Parity Error (DPE)
Not Applicable or Implemented. Hard wired to 0. Parity
(generating poisoned TLPs) is not supported on the primary
side of this device (we don't do error forwarding).
Signaled System Error (SSE)
This bit is set when this Device sends an SERR due to
detecting an ERR_FATAL or ERR_NONFATAL condition and the
SERR Enable bit in the Command register is 1. Both received
(if enabled by BCTRL1[1]) and internally detected error
messages do not affect this field.
Received Master Abort Status (RMAS)
Not Applicable or Implemented. Hard wired to 0. The concept
of a master abort does not exist on primary side of this
device.
Received Target Abort Status (RTAS)
Not Applicable or Implemented. Hard wired to 0. The concept
of a target abort does not exist on primary side of this device.
Signaled Target Abort Status (STAS)
Not Applicable or Implemented. Hard wired to 0. The concept
of a target abort does not exist on primary side of this device.
DEVSELB Timing (DEVT)
This device is not the subtractively decoded device on bus 0.
This bit field is therefore hard wired to 00 to indicate that the
device uses the fastest possible decode.
Master Data Parity Error (PMDPE)
Because the primary side of the PCIe graphic's virtual P2P
bridge is integrated with the PROCESSOR functionality there
is no scenario where this bit will get set. Because hardware
will never set this bit, it is impossible for software to have an
opportunity to clear this bit or otherwise test that it is
implemented. The PCI Local Bus Specification defines it as a
R/WC, but for our implementation an RO definition behaves
the same way and will meet all Microsoft testing
requirements.
This bit can only be set when the Parity Error Enable bit in the
PCI Command register is set.
0/1/0/PCI
6-7h
0010h
RO; RWC
16 bits
(Sheet 1 of 2)
Description
Processor Configuration Registers
Datasheet