CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 342

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

1.19.31
342
VTPOLICY - DMA Remap Engine Policy Control
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
This registers contains all the policy bits related to the DMA remap engine.
30:5
79:64
63:12
Bit
31
11:0
4
Bit
Access
RW-L-K
RW-L
Access
RO
RO-P
RO-P
RO
0000000h
00000000
Default
Default
Value
00000h
Value
0000h
000h
0b
0b
DMA Remap Engine Policy Lock-Down (DMAR_LCKDN)
This register bit protects all the DMA remap engine specific
policy configuration registers. Once this bit is set by software
all the DMA remap engine registers within the range 0xF00
to 0xFFC is read-only. This bit can only be clear through
platform reset.
Reserved
TLB Lookup Policy TLB Invalidation (LKUPPTLBINV)
DMI Intel High Definition Audio Remap Engine TLB Lookup
Policy On TLB Invalidation:
0 = Continue to perform TLB lookup to DMI Intel® High
1 = Mask all TLB Lookup to DMI Intel High Definition Audio
TLB Invalidation Window refers to the period from when the
TLB Invalidation is initiated until all the outstanding DMA
read and write cycles at the point of TLB Invalidation are
initiated are Globally Ordered.
Source Identifier (SID)
Requester-id associated with the fault condition.
This field is relevant only when the F field is Set.
Fault Info (FI)
When the Fault Reason (FR) field indicates one of the DMA-
remapping fault conditions, Bits 63:12 of this field contains
the page address in the faulted DMA request. Hardware
treat Bits 63:N as reserved (0), where N is the maximum
guest address width (MGAW) supported.
When the Fault Reason (FR) field indicates one of the
interrupt-remapping fault conditions, Bits 63:48 of this field
indicate the interrupt_index computed for the faulted
interrupt request, and Bits 47:12 are cleared.
This field is relevant only when the F field is Set.
Reserved
0/0/0/DMIVC1REMAP
FFC-FFFh
00000000h
RO; RW-L-K; RW-L
32 bits
Definition Audio remap engine during TLB Invalidation
Window.
remap engine during TLB Invalidation Window.
(Sheet 2 of 2)
(Sheet 1 of 2)
Processor Configuration Registers
Description
Description
Datasheet