CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 41

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

Processor Configuration Registers
Datasheet
Figure 9.
0xFFFFFFF
0x1FFFFF
PCI Express* Base Address
0xFFFFF
accessed. Locked transactions to the PCI Express memory mapped configuration
address space are not supported. All changes made using either access mechanism are
equivalent.
The PCI Express Enhanced Configuration Mechanism utilizes a flat memory-mapped
address space to access device configuration registers. This address space is reported
by the system firmware to the operating system. There is a register, PCIEXBAR, that
defines the base address for the block of addresses below 4 GB for the configuration
space associated with busses, devices and functions that are potentially a part of the
PCI Express root complex hierarchy. In the PCIEXBAR register there are controls to
limit the size of this reserved memory mapped space. 256 MB is the amount of address
space required to reserve space for every bus, device, and function that could possibly
exist. Options for 128 MB and 64 MB exist in order to free up those addresses for other
uses. In these cases. the number of busses and all of their associated devices and
functions are limited to 128 or 64 busses, respectively.
The PCI Express Configuration Transaction Header includes an additional four bits
(ExtendedRegisterAddress[3:0]) between the Function Number and Register Address
fields to provide indexing into the 4 KB of configuration space allocated to each
potential device. For PCI Compatible Configuration Requests, the Extended Register
Address field must be all zeros.
Memory Map to PCI Express Device Configuration Space
Just the same as with PCI devices, each device is selected based on decoded address
information that is provided as a part of the address portion of Configuration Request
packets. A PCI Express device will decode all address information fields (Bus, Device,
Function and extended address numbers) to provide access to the correct register.
0
Located by
Bus 255
Bus 1
Bus 0
0xFFFFF
0xFFFF
0x7FFF
Device 31
Device 1
Device 0
0x7FFF
0x1FFF
0xFFF
Function 7
Function 1
Function 0
0xFFF
0xFF
0x3F
PCI Compatible
PCI Compatible
Configuration
PCI Express
Space Header
Configuration
Configuration
Extended
Space
Space
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