CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 62

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

1.8.15
62
DEVEN - Device Enable
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
BIOS Optimal Default
Allows for enabling/disabling of PCI devices and functions that are within the processor.
The table below the bit definitions describes the behavior of all combinations of
transactions to devices controlled by this register. All the bits in this register are Intel
TXT Lockable.
31:15
14:13
12:12
9:9
7:4
2:2
Bit
11
10
8
3
1
0
Access
RW-L
RW-L
RW-L
RW-L
RW-L
RW-L
RO
RO
RO
RO
RO
RO
Default
Value
0h
0b
0h
0b
0b
0h
1b
0h
1b
0h
1b
1b
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Internal Graphics Engine Function 0 (D2F0EN)
0 = Bus 0 Device 2 Function 0 is disabled and hidden
1 = Bus 0 Device 2 Function 0 is enabled and visible
Reserved
PCI Express Port (D1EN)
0 = Bus 0 Device 1 Function 0 is disabled and hidden.
1 = Bus 0 Device 1 Function 0 is enabled and visible.
Host Bridge (D0EN)
Bus 0 Device 0 Function 0 may not be disabled and is
therefore hard wired to 1.
0/0/0/PCI
54-57h
0000010Bh
RW-L; RO; RW
32 bits
000000h
Processor Configuration Registers
Description
Datasheet