CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 347

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

Processor Configuration Registers
Datasheet
53:48
47:40
37:34
33:24
Bit
39
38
23
Access
RO
RO
RO
RO
RO
RO
RO
Default
Value
020h
00h
00h
0b
0b
0h
0b
Maximum Address Mask Value (MAMV)
The value in this field indicates the maximum supported value
for the Address Mask (AM) field in the Invalidation Address
(IVA_REG) register.
Number of Fault-recording Registers (NFR)
Number of fault recording registers is computed as N+1,
where N is the value reported in this field.
Implementations must support at least one fault recording
register (NFR = 0) for each DMA remapping hardware unit in
the platform.
The maximum number of fault recording registers per DMA-
remapping hardware unit is 256.
Page-Selective Invalidation Support (PSI)
0 = Hardware supports only domain and global invalidates for
1 = Hardware supports page selective, domain, and global
Reserved
Super-Page Support (SPS)
This field indicates the super page sizes supported by
hardware.
A value of 1 in any of these bits indicates the corresponding
super-page size is supported.
The super-page sizes corresponding to various bit positions
within this field are:
0: 21-bit offset to page frame (2 MB)
1: 30-bit offset to page frame (1 GB)
2: 39-bit offset to page frame (512 GB)
3: 48-bit offset to page frame (1 TB)
Fault-recording Register Offset (FRO)
This field specifies the location to the first fault recording
register relative to the register base address of this DMA-
remapping hardware unit.
If the register base address is X, and the value reported in
this field is Y, the address for the first fault recording register
is calculated as X+(16*Y).
Isochrony (ISOCH)
0 = Indicates this DMA-remapping hardware unit has no
1 = Indicates this DMA-remapping hardware unit has one or
IOTLB.
invalidates for IOTLB and hardware must support a
minimum MAMV value of 9.
critical isochronous requesters in its scope.
more critical isochronous requesters in its scope. To
guarantee isochronous performance, software must
ensure invalidation operations do not impact active DMA
streams from such requesters. This implies that when
DMA is active, software perform page-selective
invalidations (instead of coarser invalidations).
(Sheet 2 of 5)
Description
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